PATCHES: R600/SI: More cleanups for the assembler
Matt Arsenault
Matthew.Arsenault at amd.com
Fri Mar 6 15:58:57 PST 2015
On 03/06/2015 02:26 PM, Tom Stellard wrote:
> Hi,
>
> Here are some more cleanup patches that are required for the assembler.
>
> -Tom
>
> 0001-R600-SI-Fix-opcode-for-ds_read2_b64-and-ds_read2st64.patch
>
>
> From 22812d5990ead84354a35fce5f3ac58c487ffaf4 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 27 Feb 2015 22:21:27 -0500
> Subject: [PATCH 01/10] R600/SI: Fix opcode for ds_read2_b64 and
> ds_read2st64_b64
>
> ---
> lib/Target/R600/SIInstructions.td | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> index ab1f08f..289f2db 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -882,8 +882,8 @@ defm DS_WRITE2ST64_B64 : DS_Store2_Helper <0x0000004F, "ds_write2st64_b64", VReg
>
> defm DS_READ2_B32 : DS_Load2_Helper <0x00000037, "ds_read2_b32", VReg_64>;
> defm DS_READ2ST64_B32 : DS_Load2_Helper <0x00000038, "ds_read2st64_b32", VReg_64>;
> -defm DS_READ2_B64 : DS_Load2_Helper <0x00000075, "ds_read2_b64", VReg_128>;
> -defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000076, "ds_read2st64_b64", VReg_128>;
> +defm DS_READ2_B64 : DS_Load2_Helper <0x00000077, "ds_read2_b64", VReg_128>;
> +defm DS_READ2ST64_B64 : DS_Load2_Helper <0x00000078, "ds_read2st64_b64", VReg_128>;
>
> //===----------------------------------------------------------------------===//
> // MUBUF Instructions
> -- 2.0.4
My copies of the SI and CI documentation has the old values for these.
Is the public documentation wrong?
>
> 0002-R600-SI-Fix-DS-definitions-and-add-missing-instructi.patch
>
>
> From b15bcd6348dff397b8b2dc54359224afb29e5acc Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 13 Feb 2015 22:51:59 -0500
> Subject: [PATCH 02/10] R600/SI: Fix DS definitions and add missing
> instructions
>
> ---
> lib/Target/R600/SIInstrInfo.td | 62 ++++++++++++++++++-
> lib/Target/R600/SIInstructions.td | 121 +++++++++++++++++++++++++-------------
> 2 files changed, 139 insertions(+), 44 deletions(-)
>
LGTM
>
>
> 0003-R600-SI-Refactor-DS-instruction-defs.patch
>
>
> From 676284a954d79a45991b55eddaebbfcbe633a729 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Mon, 2 Mar 2015 07:48:04 -0500
> Subject: [PATCH 03/10] R600/SI: Refactor DS instruction defs
>
> ---
> lib/Target/R600/SIInstrFormats.td | 6 +
> lib/Target/R600/SIInstrInfo.td | 264 ++++++++++++++------------------------
> lib/Target/R600/SIInstructions.td | 48 ++++---
> 3 files changed, 130 insertions(+), 188 deletions(-)
>
LGTM
> 0004-R600-SI-Move-gds-operand-to-the-end-of-operand-list.patch
>
>
> From 3adb27413a73678ea95f8fe241bbaddbabfe58de Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 5 Mar 2015 15:54:17 -0500
> Subject: [PATCH 04/10] R600/SI: Move gds operand to the end of operand list
>
> Also print it in the assembly string.
> ---
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp | 6 +++
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h | 1 +
> lib/Target/R600/SIInstrInfo.td | 49 ++++++++++++-----------
> lib/Target/R600/SIInstructions.td | 18 ++++-----
> lib/Target/R600/SILoadStoreOptimizer.cpp | 4 +-
> 5 files changed, 44 insertions(+), 34 deletions(-)
LGTM
>
> 0005-R600-SI-Add-32-bit-encoding-of-v_cndmask_b32.patch
>
>
> From 81b5cdbefad18dca0dcd32cdf0fd17b8003f8856 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Tue, 30 Dec 2014 07:03:33 -0500
> Subject: [PATCH 05/10] R600/SI: Add 32-bit encoding of v_cndmask_b32
>
> This was done by refactoring the v_cndmask_b32 tablegen definition
> to use inherit from VOP2Inst.
> ---
> lib/Target/R600/SIInstrInfo.td | 5 +++++
> lib/Target/R600/SIInstructions.td | 21 +++++++++++++++------
> lib/Target/R600/SIShrinkInstructions.cpp | 2 ++
> 3 files changed, 22 insertions(+), 6 deletions(-)
LGTM
> diff --git a/lib/Target/R600/SIShrinkInstructions.cpp b/lib/Target/R600/SIShrinkInstructions.cpp
> index 97bbd78..2733448 100644
> --- a/lib/Target/R600/SIShrinkInstructions.cpp
> +++ b/lib/Target/R600/SIShrinkInstructions.cpp
> @@ -88,6 +88,8 @@ static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
>
> const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
> // Can't shrink instruction with three operands.
> + // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
> + // a special case for it.
It might be useful to elaborate more why here
> if (Src2)
> return false;
>
> -- 2.0.4
>
> 0006-R600-SI-Move-kill-flag-to-second-instruction-when-sp.patch
>
>
> From 5c196e65686f13179c38e5d4ab0cdedf08d8b0db Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Tue, 24 Feb 2015 21:06:59 -0500
> Subject: [PATCH 06/10] R600/SI: Move kill flag to second instruction when
> splitting SMRD
>
> This fixes a machine verifier error in the salu-to-valu.ll, which
> would have been exposed by a future commit.
> ---
> lib/Target/R600/SIInstrInfo.cpp | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
LGTM
> 0007-R600-SI-Re-order-MUBUF-operands-to-match-asm-strings.patch
>
>
> From 0e6521fe1823c400e7e4a4d7eb0233a62b582101 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 19 Feb 2015 12:49:07 -0500
> Subject: [PATCH 07/10] R600/SI: Re-order MUBUF operands to match asm strings.
>
> ---
> lib/Target/R600/SIInstrInfo.cpp | 7 +++----
> lib/Target/R600/SIInstrInfo.td | 16 ++++++++--------
> lib/Target/R600/SIInstructions.td | 16 ++++++++--------
> 3 files changed, 19 insertions(+), 20 deletions(-)
LGTM
>
> 0008-R600-SI-Add-_IDXEN-and-_BOTHEN-variants-for-buffer_s.patch
>
>
> From 0f9aaafe4fc91d2dd5e941f98d0ecbd79443d777 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Thu, 19 Feb 2015 13:50:08 -0500
> Subject: [PATCH 08/10] R600/SI: Add _IDXEN and _BOTHEN variants for
> buffer_store
>
> ---
> lib/Target/R600/SIInstrInfo.td | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
LGTM. I was thinking it would be better to rename the _BOTHENs to be
_IDXEN_OFFEN to be clearer
> 0009-R600-SI-Remove-_e32-and-_e64-suffixes-from-mnemonics.patch
>
>
> From 8992c34de76028f8ed9ebaf8e62ee17777e21198 Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 20 Feb 2015 11:53:52 -0500
> Subject: [PATCH 09/10] R600/SI: Remove _e32 and _e64 suffixes from mnemonics
>
> Instead print them as part of the $dst operand. The AsmMatcher
> requires the 32-bit and 64-bit encodings have the same mnemonic in
> order to parse them correctly.
> ---
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp | 10 +++++
> lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h | 1 +
> lib/Target/R600/SIInstrFormats.td | 5 ++-
> lib/Target/R600/SIInstrInfo.td | 48 ++++++++++++-----------
> lib/Target/R600/SIInstructions.td | 2 +-
> test/CodeGen/R600/madak.ll | 4 +-
> test/CodeGen/R600/madmk.ll | 2 +-
> test/CodeGen/R600/uint_to_fp.ll | 2 +-
> 8 files changed, 45 insertions(+), 29 deletions(-)
>
LGTM
>
>
> 0010-R600-SI-Don-t-print-scc-reg-in-sopc-assembly-string.patch
>
>
> From a272d10d47a71823b31064bdea1ef3203e9e03ca Mon Sep 17 00:00:00 2001
> From: Tom Stellard<thomas.stellard at amd.com>
> Date: Fri, 20 Feb 2015 19:48:00 -0500
> Subject: [PATCH 10/10] R600/SI: Don't print scc reg in sopc assembly string
>
> This is how the proprietary driver prints sopc instructions.
> ---
> lib/Target/R600/SIInstrInfo.td | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
LGTM
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