PATCH: R600/SI: Instruction cleanups for the assembler
Tom Stellard
tom at stellard.net
Fri Mar 6 12:53:26 PST 2015
> >
> > 0002-R600-SI-Add-32-bit-encoding-of-v_cndmask_b32.patch
> >
> >
> > From f584799d16a0f8bd09503ef048a1800e56dc37fd Mon Sep 17 00:00:00 2001
> > From: Tom Stellard<thomas.stellard at amd.com>
> > Date: Tue, 30 Dec 2014 07:03:33 -0500
> > Subject: [PATCH 2/8] R600/SI: Add 32-bit encoding of v_cndmask_b32
> >
> > This was done by refactoring the v_cndmask_b32 tablegen definition
> > to use inherit from VOP2Inst.
> > ---
> > lib/Target/R600/SIInstrInfo.td | 5 +++++
> > lib/Target/R600/SIInstructions.td | 21 +++++++++++++++------
> > lib/Target/R600/SIShrinkInstructions.cpp | 2 ++
> > 3 files changed, 22 insertions(+), 6 deletions(-)
> >
> > diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> > index bcb7655..9c8d1e6 100644
> > --- a/lib/Target/R600/SIInstrInfo.td
> > +++ b/lib/Target/R600/SIInstrInfo.td
> > @@ -799,6 +799,11 @@ def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
> > def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
> > def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
> > def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
> > +def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
> > + let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
> > + let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
> > + let Asm64 = " $dst, $src0, $src1, $src2";
> > +}
> Why untyped instead of i1?
>
Type type doesn't matter here, because we are defining custom ins.
> > 0008-R600-SI-Remove-_e32-and-_e64-suffixes-from-mnemonics.patch
> >
> >
> > From b03b2f918a0a1b8681153248fe9b19f725f4b1e1 Mon Sep 17 00:00:00 2001
> > From: Tom Stellard<thomas.stellard at amd.com>
> > Date: Fri, 20 Feb 2015 11:53:52 -0500
> > Subject: [PATCH 8/8] R600/SI: Remove _e32 and _e64 suffixes from mnemonics
> >
> > Instead print them as part of the $dst operand. With this patch,
> > all instructions are printed the same as before, with the exception
> > of the madmk and madak instructions, which now have the _e32 suffix.
> >
> > The AsmMatcher requires the 32-bit and 64-bit encodings have the same
> > mnemonic in order to parse them correctly.
> > ---
> > lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp | 10 +++++
> > lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h | 1 +
> > lib/Target/R600/SIInstrFormats.td | 5 ++-
> > lib/Target/R600/SIInstrInfo.td | 48 ++++++++++++-----------
> > lib/Target/R600/SIInstructions.td | 2 +-
> > test/CodeGen/R600/madak.ll | 4 +-
> > test/CodeGen/R600/madmk.ll | 2 +-
> > test/CodeGen/R600/uint_to_fp.ll | 2 +-
> > 8 files changed, 45 insertions(+), 29 deletions(-)
> >
> > diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> > index b66ed10..f87ec3c 100644
> > --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> > +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
> > @@ -208,6 +208,16 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
> > O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
> > }
> >
> > +void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
> > + raw_ostream &O) {
> > + if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
> > + O << "_e64 ";
> > + else
> > + O << "_e32 ";
> > +
> > + printOperand(MI, OpNo, O);
> > +}
> > +
> The operand seems like a weird place to put this. I thought the plan was
> to remove these suffixes? They are useful for debugging / tests, but the
> shader compiler doesn't use them.
>
I've decided to keep them, I think they are really useful for debugging
and make the code easier to read.
> If you removed the space here, you wouldn't need to change all the asm
> strings to not also add it.
I need to remove the space every, because the _e32 suffix is the first
part of $dst. For example:
$dst='_e32 v0'
v_add_f32$dst -> v_add_f32_e32 v0
-Tom
> > void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) {
> > int32_t SImm = static_cast<int32_t>(Imm);
> > if (SImm >= -16 && SImm <= 64) {
> > diff --git a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> > index 1d43c7a..0bedc25 100644
> > --- a/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> > +++ b/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
> > @@ -48,6 +48,7 @@ private:
> > void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> > void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> > void printRegOperand(unsigned RegNo, raw_ostream &O);
> > + void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> > void printImmediate32(uint32_t I, raw_ostream &O);
> > void printImmediate64(uint64_t I, raw_ostream &O);
> > void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
> > diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td
> > index c90c741..323d7b4 100644
> > --- a/lib/Target/R600/SIInstrFormats.td
> > +++ b/lib/Target/R600/SIInstrFormats.td
> > @@ -83,6 +83,9 @@ class Enc64 {
> > int Size = 8;
> > }
> >
> > +class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">;
> > +def VOPDstVCC : VOPDstOperand <VCCReg>;
> > +
> > let Uses = [EXEC] in {
> >
> > class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
> > @@ -96,7 +99,7 @@ class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
> > }
> >
> > class VOPCCommon <dag ins, string asm, list<dag> pattern> :
> > - VOPAnyCommon <(outs VCCReg:$dst), ins, asm, pattern> {
> > + VOPAnyCommon <(outs VOPDstVCC:$dst), ins, asm, pattern> {
> >
> > let DisableEncoding = "$dst";
> > let VOPC = 1;
> > diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> > index de6ad67..3eec024 100644
> > --- a/lib/Target/R600/SIInstrInfo.td
> > +++ b/lib/Target/R600/SIInstrInfo.td
> > @@ -284,6 +284,8 @@ def ClampMod : Operand <i1> {
> >
> > } // End OperandType = "OPERAND_IMMEDIATE"
> >
> > +def VOPDstS64 : VOPDstOperand <SReg_64>;
> > +
> > //===----------------------------------------------------------------------===//
> > // Complex patterns
> > //===----------------------------------------------------------------------===//
> > @@ -637,9 +639,9 @@ class getNumSrcArgs<ValueType Src1, ValueType Src2> {
> > // Returns the register class to use for the destination of VOP[123C]
> > // instructions for the given VT.
> > class getVALUDstForVT<ValueType VT> {
> > - RegisterClass ret = !if(!eq(VT.Size, 32), VGPR_32,
> > - !if(!eq(VT.Size, 64), VReg_64,
> > - SReg_64)); // else VT == i1
> > + RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
> > + !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
> > + VOPDstOperand<SReg_64>)); // else VT == i1
> > }
> >
> > // Returns the register class to use for source 0 of VOP[12C]
> > @@ -717,7 +719,7 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
> > class getAsm32 <int NumSrcArgs> {
> > string src1 = ", $src1";
> > string src2 = ", $src2";
> > - string ret = " $dst, $src0"#
> > + string ret = "$dst, $src0"#
> > !if(!eq(NumSrcArgs, 1), "", src1)#
> > !if(!eq(NumSrcArgs, 3), src2, "");
> > }
> > @@ -733,7 +735,7 @@ class getAsm64 <int NumSrcArgs, bit HasModifiers> {
> > string ret =
> > !if(!eq(HasModifiers, 0),
> > getAsm32<NumSrcArgs>.ret,
> > - " $dst, "#src0#src1#src2#"$clamp"#"$omod");
> > + "$dst, "#src0#src1#src2#"$clamp"#"$omod");
> > }
> >
> >
> > @@ -745,7 +747,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
> > field ValueType Src0VT = ArgVT[1];
> > field ValueType Src1VT = ArgVT[2];
> > field ValueType Src2VT = ArgVT[3];
> > - field RegisterClass DstRC = getVALUDstForVT<DstVT>.ret;
> > + field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
> > field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
> > field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
> > field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
> > @@ -761,7 +763,7 @@ class VOPProfile <list<ValueType> _ArgVT> {
> > field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
> > HasModifiers>.ret;
> >
> > - field string Asm32 = "_e32"#getAsm32<NumSrcArgs>.ret;
> > + field string Asm32 = getAsm32<NumSrcArgs>.ret;
> > field string Asm64 = getAsm64<NumSrcArgs, HasModifiers>.ret;
> > }
> >
> > @@ -788,12 +790,12 @@ def VOP_I32_I32_I32_VCC : VOPProfile <[i32, i32, i32, untyped]> {
> >
> > def VOP_I1_F32_I32 : VOPProfile <[i1, f32, i32, untyped]> {
> > let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
> > - let Asm64 = " $dst, $src0_modifiers, $src1";
> > + let Asm64 = "$dst, $src0_modifiers, $src1";
> > }
> >
> > def VOP_I1_F64_I32 : VOPProfile <[i1, f64, i32, untyped]> {
> > let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
> > - let Asm64 = " $dst, $src0_modifiers, $src1";
> > + let Asm64 = "$dst, $src0_modifiers, $src1";
> > }
> >
> > def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
> > @@ -802,13 +804,13 @@ def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
> > def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
> > let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VCCReg:$src2);
> > let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
> > - let Asm64 = " $dst, $src0, $src1, $src2";
> > + let Asm64 = "$dst, $src0, $src1, $src2";
> > }
> >
> > def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
> > def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
> > field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
> > - field string Asm = " $dst, $src0, $vsrc1, $src2";
> > + field string Asm = "$dst, $src0, $vsrc1, $src2";
> > }
> > def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
> > def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
> > @@ -1091,7 +1093,7 @@ multiclass VOP1_Helper <vop1 op, string opName, dag outs,
> >
> > defm _e32 : VOP1_m <op, outs, ins32, opName#asm32, pat32, opName>;
> >
> > - defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
> > + defm _e64 : VOP3_1_m <op, outs, ins64, opName#asm64, pat64, opName, HasMods>;
> > }
> >
> > multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
> > @@ -1126,7 +1128,7 @@ multiclass VOP2_Helper <vop2 op, string opName, dag outs,
> > defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
> >
> > defm _e64 : VOP3_2_m <op,
> > - outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
> > + outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
> > >;
> > }
> >
> > @@ -1150,7 +1152,7 @@ multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
> > string revOp = opName> {
> > defm _e32 : VOP2SI_m <op, P.Outs, P.Ins32, P.Asm32, [], opName, revOp>;
> >
> > - defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#"_e64"#P.Asm64,
> > + defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
> > !if(P.HasModifiers,
> > [(set P.DstVT:$dst,
> > (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
> > @@ -1168,7 +1170,7 @@ multiclass VOP2b_Helper <vop2 op, string opName, dag outs,
> > defm _e32 : VOP2_m <op, outs, ins32, asm32, pat32, opName, revOp>;
> >
> > defm _e64 : VOP3b_2_m <op,
> > - outs, ins64, opName#"_e64"#asm64, pat64, opName, revOp, HasMods
> > + outs, ins64, opName#asm64, pat64, opName, revOp, HasMods
> > >;
> > }
> >
> > @@ -1194,7 +1196,7 @@ multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
> > string revOp, bit HasMods> {
> > defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOp>;
> >
> > - defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
> > + defm _e64 : VOP3_2_m <op, outs, ins64, opName#asm64, pat64, opName,
> > revOp, HasMods>;
> > }
> >
> > @@ -1260,7 +1262,7 @@ multiclass VOPC_Helper <vopc op, string opName,
> > bit HasMods, bit DefExec> {
> > defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
> >
> > - defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
> > + defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
> > opName, HasMods, DefExec>;
> > }
> >
> > @@ -1272,7 +1274,7 @@ multiclass VOPC_Class_Helper <vopc op, string opName,
> > bit HasMods, bit DefExec> {
> > defm _e32 : VOPC_m <op, (outs), ins32, opName#asm32, pat32, opName, DefExec>;
> >
> > - defm _e64 : VOP3_C_m <op, out64, ins64, opName#"_e64"#asm64, pat64,
> > + defm _e64 : VOP3_C_m <op, out64, ins64, opName#asm64, pat64,
> > opName, HasMods, DefExec>,
> > VOP3DisableModFields<1, 0, 0>;
> > }
> > @@ -1282,7 +1284,7 @@ multiclass VOPCInst <vopc op, string opName,
> > bit DefExec = 0> : VOPC_Helper <
> > op, opName,
> > P.Ins32, P.Asm32, [],
> > - (outs SReg_64:$dst), P.Ins64, P.Asm64,
> > + (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
> > !if(P.HasModifiers,
> > [(set i1:$dst,
> > (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
> > @@ -1297,7 +1299,7 @@ multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
> > bit DefExec = 0> : VOPC_Class_Helper <
> > op, opName,
> > P.Ins32, P.Asm32, [],
> > - (outs SReg_64:$dst), P.Ins64, P.Asm64,
> > + (outs VOPDstS64:$dst), P.Ins64, P.Asm64,
> > !if(P.HasModifiers,
> > [(set i1:$dst,
> > (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
> > @@ -1337,7 +1339,7 @@ multiclass VOPCX_I64 <vopc op, string opName, PatLeaf cond = COND_NULL> :
> >
> > multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
> > list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m <
> > - op, outs, ins, opName#asm, pat, opName, NumSrcArgs, HasMods
> > + op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
> > >;
> >
> > multiclass VOPC_CLASS_F32 <vopc op, string opName> :
> > @@ -1354,7 +1356,7 @@ multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
> >
> > multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
> > SDPatternOperator node = null_frag> : VOP3_Helper <
> > - op, opName, P.Outs, P.Ins64, P.Asm64,
> > + op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
> > !if(!eq(P.NumSrcArgs, 3),
> > !if(P.HasModifiers,
> > [(set P.DstVT:$dst,
> > @@ -1386,7 +1388,7 @@ multiclass VOP3_VCC_Inst <vop3 op, string opName,
> > VOPProfile P,
> > SDPatternOperator node = null_frag> : VOP3_Helper <
> > op, opName,
> > - P.Outs,
> > + (outs P.DstRC.RegClass:$dst),
> > (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
> > InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
> > InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
> > diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
> > index 6e3fa51..67a2675 100644
> > --- a/lib/Target/R600/SIInstructions.td
> > +++ b/lib/Target/R600/SIInstructions.td
> > @@ -1440,7 +1440,7 @@ multiclass V_CNDMASK <vop2 op, string name> {
> >
> > defm _e64 : VOP3_m <
> > op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64,
> > - name#"_e64"#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3>;
> > + name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3>;
> > }
> >
> > defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">;
> > diff --git a/test/CodeGen/R600/madak.ll b/test/CodeGen/R600/madak.ll
> > index 505a49b..ac73eae 100644
> > --- a/test/CodeGen/R600/madak.ll
> > +++ b/test/CodeGen/R600/madak.ll
> > @@ -9,7 +9,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone
> > ; GCN-LABEL: {{^}}madak_f32:
> > ; GCN: buffer_load_dword [[VA:v[0-9]+]]
> > ; GCN: buffer_load_dword [[VB:v[0-9]+]]
> > -; GCN: v_madak_f32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000
> > +; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VB]], [[VA]], 0x41200000
> > define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind {
> > %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
> > %in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
> > @@ -63,7 +63,7 @@ define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1
> >
> > ; GCN-LABEL: {{^}}madak_m_inline_imm_f32:
> > ; GCN: buffer_load_dword [[VA:v[0-9]+]]
> > -; GCN: v_madak_f32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
> > +; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000
> > define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind {
> > %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
> > %in.a.gep = getelementptr float addrspace(1)* %in.a, i32 %tid
> > diff --git a/test/CodeGen/R600/madmk.ll b/test/CodeGen/R600/madmk.ll
> > index 249e48e..b787edd 100644
> > --- a/test/CodeGen/R600/madmk.ll
> > +++ b/test/CodeGen/R600/madmk.ll
> > @@ -7,7 +7,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone
> > ; GCN-LABEL: {{^}}madmk_f32:
> > ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
> > ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
> > -; GCN: v_madmk_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
> > +; GCN: v_madmk_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
> > define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind {
> > %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone
> > %gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
> > diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll
> > index 1c8a175..8eebcbc 100644
> > --- a/test/CodeGen/R600/uint_to_fp.ll
> > +++ b/test/CodeGen/R600/uint_to_fp.ll
> > @@ -50,7 +50,7 @@ define void @uint_to_fp_v4i32_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i32>
> > ; R600: MULADD_IEEE
> > ; SI: v_cvt_f32_u32_e32
> > ; SI: v_cvt_f32_u32_e32
> > -; SI: v_madmk_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000
> > +; SI: v_madmk_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x4f800000
> > ; SI: s_endpgm
> > define void @uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) {
> > entry:
> > -- 2.0.4
> >
> >
> > _______________________________________________
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> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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