[PATCH] CodeGenPrepare: Avoid and/or i1 in select conditions.

[hfinkel at anl.gov]

REPOSITORY
  rL LLVM

================
Comment at: include/llvm/Target/TargetLowering.h:1113
@@ +1112,3 @@
+    // Only do the transform if the value fits into one register.
+    return getNumRegisters(Context, VT) <= 1;
+  }
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> Tweak the callback to not cover types that need multiple registers as those will typically be broken down into multiple select-like instructions.

Normally, to check this condition, we'd just use:
  isTypeLegal(VT)

http://reviews.llvm.org/D7622

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