[llvm] r231249 - [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator

[Jozef Kolek]

Author: jkolek
Date: Wed Mar  4 09:47:42 2015
New Revision: 231249

URL: http://llvm.org/viewvc/llvm-project?rev=231249&view=rev
Log:
[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator

Differential Revision: http://reviews.llvm.org/D7609

Added:
    llvm/trunk/test/CodeGen/Mips/micromips-addu16.ll
    llvm/trunk/test/CodeGen/Mips/micromips-subu16.ll
Modified:
    llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=231249&r1=231248&r2=231249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed Mar  4 09:47:42 2015
@@ -642,8 +642,10 @@ let DecoderNamespace = "MicroMips", Pred
                      LW_FM_MM<0xc>;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
-  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
-  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
+  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+                 ADD_FM_MM<0, 0x150>;
+  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+                 ADD_FM_MM<0, 0x1d0>;
   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=231249&r1=231248&r2=231249&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Mar  4 09:47:42 2015
@@ -1140,12 +1140,13 @@ def XORi  : MMRel, ArithLogicI<"xori", u
                                xor>,
             ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
-
+let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
+}
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;

Added: llvm/trunk/test/CodeGen/Mips/micromips-addu16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-addu16.ll?rev=231249&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-addu16.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-addu16.ll Wed Mar  4 09:47:42 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %add = add nsw i32 %0, %1
+  store i32 %add, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: addu16

Added: llvm/trunk/test/CodeGen/Mips/micromips-subu16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/micromips-subu16.ll?rev=231249&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/micromips-subu16.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/micromips-subu16.ll Wed Mar  4 09:47:42 2015
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32, i32* %b, align 4
+  %1 = load i32, i32* %c, align 4
+  %sub = sub nsw i32 %0, %1
+  store i32 %sub, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: subu16