[llvm] r231085 - [AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).

[Chad Rosier]

Author: mcrosier
Date: Tue Mar  3 11:31:01 2015
New Revision: 231085

URL: http://llvm.org/viewvc/llvm-project?rev=231085&view=rev
Log:
[AArch64] When combining constant mul of -3, prefer (sub x, (shl x, N)).

This change only effects codegen when the constant is -3.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=231085&r1=231084&r2=231085&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Mar  3 11:31:01 2015
@@ -6895,6 +6895,15 @@ static SDValue performMulCombine(SDNode
                            N->getOperand(0));
       }
     } else {
+      // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
+      APInt VNP1 = -Value + 1;
+      if (VNP1.isPowerOf2()) {
+        SDValue ShiftedVal =
+            DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
+                        DAG.getConstant(VNP1.logBase2(), MVT::i64));
+        return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
+                           ShiftedVal);
+      }
       // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
       APInt VNM1 = -Value - 1;
       if (VNM1.isPowerOf2()) {
@@ -6905,15 +6914,6 @@ static SDValue performMulCombine(SDNode
             DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
         return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
       }
-      // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
-      APInt VNP1 = -Value + 1;
-      if (VNP1.isPowerOf2()) {
-        SDValue ShiftedVal =
-            DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
-                        DAG.getConstant(VNP1.logBase2(), MVT::i64));
-        return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
-                           ShiftedVal);
-      }
     }
   }
   return SDValue();

Modified: llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll?rev=231085&r1=231084&r2=231085&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/mul_pow2.ll Tue Mar  3 11:31:01 2015
@@ -74,8 +74,7 @@ define i32 @ntest2(i32 %x) {
 
 define i32 @ntest3(i32 %x) {
 ; CHECK-LABEL: ntest3
-; CHECK: add {{w[0-9]+}}, w0, w0, lsl #1
-; CHECK: neg w0, {{w[0-9]+}}
+; CHECK: sub w0, w0, w0, lsl #2
 
   %mul = mul nsw i32 %x, -3
   ret i32 %mul