[PATCH] [PPC64] Add 64-bit Vector Integer Arithmetic Instructions

[Bill Schmidt]

Looks like you added some vector compares as well.  That should be called out in the description.

Additional comments inline.


================
Comment at: include/llvm/IR/IntrinsicsPowerPC.td:102
@@ -97,1 +101,3 @@
+                          [llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
+                          [IntrNoMem]>;
 
----------------
You and Nemanja will have a conflict here -- first to commit wins. ;)

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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:6531
@@ -6519,1 +6530,3 @@
+/// we can rely on the generator of the builtin to check for this condition
+/// and only generate the intrinsic when it is legal to do so.
 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
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Hm.  Nonetheless we probably want to fail gracefully if somebody writes an IR test that uses this builtin with -mattr=-p8altivec.  If you can convince me we will fail gracefully before getting here under those circumstances, I'm ok with it, but otherwise an assert is probably in order.

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Comment at: lib/Target/PowerPC/PPCSchedule.td:376
@@ -375,3 +375,3 @@
 //    tlbie      IIC_LdStDCBF
 //    tlbsync    IIC_SprTLBSYNC
 //    tw         IIC_IntTrapW
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Question for Hal:  Why do we have this table of comments that needs to be updated as new instructions are added?  Not sure whether it provides value, and it's an extra bit of noise in the process.  Just curious.  Others have noted that this list is not currently complete in any case.  I'd personally rather just see it go away.

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Comment at: test/CodeGen/PowerPC/vec_add_sub_doubleword.ll:39
@@ +38,3 @@
+;        set up the vector register). I think a better way would be to
+;        splat the value into a vector register.
+}
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Please add this to the README.ALTIVEC file if you haven't already.

http://reviews.llvm.org/D7959

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