[llvm] r229613 - R600/SI: Consistently capitalize encoding field names
Matt Arsenault
Matthew.Arsenault at amd.com
Tue Feb 17 18:15:35 PST 2015
Author: arsenm
Date: Tue Feb 17 20:15:35 2015
New Revision: 229613
URL: http://llvm.org/viewvc/llvm-project?rev=229613&view=rev
Log:
R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change
them all to be consistently lowercase.
Now, non-encoding fields and convenience bits are capitalized.
Also remove weird looking empty line in some of the formats.
Modified:
llvm/trunk/lib/Target/R600/SIInstrFormats.td
llvm/trunk/lib/Target/R600/SIInstrInfo.td
llvm/trunk/lib/Target/R600/VIInstrFormats.td
Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=229613&r1=229612&r2=229613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Tue Feb 17 20:15:35 2015
@@ -74,13 +74,11 @@ class InstSI <dag outs, dag ins, string
}
class Enc32 {
-
field bits<32> Inst;
int Size = 4;
}
class Enc64 {
-
field bits<64> Inst;
int Size = 8;
}
@@ -139,53 +137,48 @@ class VOP3Common <dag outs, dag ins, str
//===----------------------------------------------------------------------===//
class SOP1e <bits<8> op> : Enc32 {
+ bits<7> sdst;
+ bits<8> ssrc0;
- bits<7> SDST;
- bits<8> SSRC0;
-
- let Inst{7-0} = SSRC0;
+ let Inst{7-0} = ssrc0;
let Inst{15-8} = op;
- let Inst{22-16} = SDST;
+ let Inst{22-16} = sdst;
let Inst{31-23} = 0x17d; //encoding;
}
class SOP2e <bits<7> op> : Enc32 {
+ bits<7> sdst;
+ bits<8> ssrc0;
+ bits<8> ssrc1;
- bits<7> SDST;
- bits<8> SSRC0;
- bits<8> SSRC1;
-
- let Inst{7-0} = SSRC0;
- let Inst{15-8} = SSRC1;
- let Inst{22-16} = SDST;
+ let Inst{7-0} = ssrc0;
+ let Inst{15-8} = ssrc1;
+ let Inst{22-16} = sdst;
let Inst{29-23} = op;
let Inst{31-30} = 0x2; // encoding
}
class SOPCe <bits<7> op> : Enc32 {
+ bits<8> ssrc0;
+ bits<8> ssrc1;
- bits<8> SSRC0;
- bits<8> SSRC1;
-
- let Inst{7-0} = SSRC0;
- let Inst{15-8} = SSRC1;
+ let Inst{7-0} = ssrc0;
+ let Inst{15-8} = ssrc1;
let Inst{22-16} = op;
let Inst{31-23} = 0x17e;
}
class SOPKe <bits<5> op> : Enc32 {
+ bits <7> sdst;
+ bits <16> simm16;
- bits <7> SDST;
- bits <16> SIMM16;
-
- let Inst{15-0} = SIMM16;
- let Inst{22-16} = SDST;
+ let Inst{15-0} = simm16;
+ let Inst{22-16} = sdst;
let Inst{27-23} = op;
let Inst{31-28} = 0xb; //encoding
}
class SOPPe <bits<7> op> : Enc32 {
-
bits <16> simm16;
let Inst{15-0} = simm16;
@@ -194,15 +187,14 @@ class SOPPe <bits<7> op> : Enc32 {
}
class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
+ bits<7> sdst;
+ bits<7> sbase;
+ bits<8> offset;
- bits<7> SDST;
- bits<7> SBASE;
- bits<8> OFFSET;
-
- let Inst{7-0} = OFFSET;
+ let Inst{7-0} = offset;
let Inst{8} = imm;
- let Inst{14-9} = SBASE{6-1};
- let Inst{21-15} = SDST;
+ let Inst{14-9} = sbase{6-1};
+ let Inst{21-15} = sdst;
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
}
@@ -286,31 +278,28 @@ class SMRD <dag outs, dag ins, string as
//===----------------------------------------------------------------------===//
class VOP1e <bits<8> op> : Enc32 {
+ bits<8> vdst;
+ bits<9> src0;
- bits<8> VDST;
- bits<9> SRC0;
-
- let Inst{8-0} = SRC0;
+ let Inst{8-0} = src0;
let Inst{16-9} = op;
- let Inst{24-17} = VDST;
+ let Inst{24-17} = vdst;
let Inst{31-25} = 0x3f; //encoding
}
class VOP2e <bits<6> op> : Enc32 {
+ bits<8> vdst;
+ bits<9> src0;
+ bits<8> vsrc1;
- bits<8> VDST;
- bits<9> SRC0;
- bits<8> VSRC1;
-
- let Inst{8-0} = SRC0;
- let Inst{16-9} = VSRC1;
- let Inst{24-17} = VDST;
+ let Inst{8-0} = src0;
+ let Inst{16-9} = vsrc1;
+ let Inst{24-17} = vdst;
let Inst{30-25} = op;
let Inst{31} = 0x0; //encoding
}
class VOP3e <bits<9> op> : Enc64 {
-
bits<8> dst;
bits<2> src0_modifiers;
bits<9> src0;
@@ -338,7 +327,6 @@ class VOP3e <bits<9> op> : Enc64 {
}
class VOP3be <bits<9> op> : Enc64 {
-
bits<8> vdst;
bits<2> src0_modifiers;
bits<9> src0;
@@ -363,33 +351,30 @@ class VOP3be <bits<9> op> : Enc64 {
}
class VOPCe <bits<8> op> : Enc32 {
+ bits<9> src0;
+ bits<8> vsrc1;
- bits<9> SRC0;
- bits<8> VSRC1;
-
- let Inst{8-0} = SRC0;
- let Inst{16-9} = VSRC1;
+ let Inst{8-0} = src0;
+ let Inst{16-9} = vsrc1;
let Inst{24-17} = op;
let Inst{31-25} = 0x3e;
}
class VINTRPe <bits<2> op> : Enc32 {
-
- bits<8> VDST;
- bits<8> VSRC;
- bits<2> ATTRCHAN;
- bits<6> ATTR;
-
- let Inst{7-0} = VSRC;
- let Inst{9-8} = ATTRCHAN;
- let Inst{15-10} = ATTR;
+ bits<8> vdst;
+ bits<8> vsrc;
+ bits<2> attrchan;
+ bits<6> attr;
+
+ let Inst{7-0} = vsrc;
+ let Inst{9-8} = attrchan;
+ let Inst{15-10} = attr;
let Inst{17-16} = op;
- let Inst{25-18} = VDST;
+ let Inst{25-18} = vdst;
let Inst{31-26} = 0x32; // encoding
}
class DSe <bits<8> op> : Enc64 {
-
bits<8> vdst;
bits<1> gds;
bits<8> addr;
@@ -410,7 +395,6 @@ class DSe <bits<8> op> : Enc64 {
}
class MUBUFe <bits<7> op> : Enc64 {
-
bits<12> offset;
bits<1> offen;
bits<1> idxen;
@@ -441,67 +425,65 @@ class MUBUFe <bits<7> op> : Enc64 {
}
class MTBUFe <bits<3> op> : Enc64 {
+ bits<8> vdata;
+ bits<12> offset;
+ bits<1> offen;
+ bits<1> idxen;
+ bits<1> glc;
+ bits<1> addr64;
+ bits<4> dfmt;
+ bits<3> nfmt;
+ bits<8> vaddr;
+ bits<7> srsrc;
+ bits<1> slc;
+ bits<1> tfe;
+ bits<8> soffset;
- bits<8> VDATA;
- bits<12> OFFSET;
- bits<1> OFFEN;
- bits<1> IDXEN;
- bits<1> GLC;
- bits<1> ADDR64;
- bits<4> DFMT;
- bits<3> NFMT;
- bits<8> VADDR;
- bits<7> SRSRC;
- bits<1> SLC;
- bits<1> TFE;
- bits<8> SOFFSET;
-
- let Inst{11-0} = OFFSET;
- let Inst{12} = OFFEN;
- let Inst{13} = IDXEN;
- let Inst{14} = GLC;
- let Inst{15} = ADDR64;
+ let Inst{11-0} = offset;
+ let Inst{12} = offen;
+ let Inst{13} = idxen;
+ let Inst{14} = glc;
+ let Inst{15} = addr64;
let Inst{18-16} = op;
- let Inst{22-19} = DFMT;
- let Inst{25-23} = NFMT;
+ let Inst{22-19} = dfmt;
+ let Inst{25-23} = nfmt;
let Inst{31-26} = 0x3a; //encoding
- let Inst{39-32} = VADDR;
- let Inst{47-40} = VDATA;
- let Inst{52-48} = SRSRC{6-2};
- let Inst{54} = SLC;
- let Inst{55} = TFE;
- let Inst{63-56} = SOFFSET;
+ let Inst{39-32} = vaddr;
+ let Inst{47-40} = vdata;
+ let Inst{52-48} = srsrc{6-2};
+ let Inst{54} = slc;
+ let Inst{55} = tfe;
+ let Inst{63-56} = soffset;
}
class MIMGe <bits<7> op> : Enc64 {
+ bits<8> vdata;
+ bits<4> dmask;
+ bits<1> unorm;
+ bits<1> glc;
+ bits<1> da;
+ bits<1> r128;
+ bits<1> tfe;
+ bits<1> lwe;
+ bits<1> slc;
+ bits<8> vaddr;
+ bits<7> srsrc;
+ bits<7> ssamp;
- bits<8> VDATA;
- bits<4> DMASK;
- bits<1> UNORM;
- bits<1> GLC;
- bits<1> DA;
- bits<1> R128;
- bits<1> TFE;
- bits<1> LWE;
- bits<1> SLC;
- bits<8> VADDR;
- bits<7> SRSRC;
- bits<7> SSAMP;
-
- let Inst{11-8} = DMASK;
- let Inst{12} = UNORM;
- let Inst{13} = GLC;
- let Inst{14} = DA;
- let Inst{15} = R128;
- let Inst{16} = TFE;
- let Inst{17} = LWE;
+ let Inst{11-8} = dmask;
+ let Inst{12} = unorm;
+ let Inst{13} = glc;
+ let Inst{14} = da;
+ let Inst{15} = r128;
+ let Inst{16} = tfe;
+ let Inst{17} = lwe;
let Inst{24-18} = op;
- let Inst{25} = SLC;
+ let Inst{25} = slc;
let Inst{31-26} = 0x3c;
- let Inst{39-32} = VADDR;
- let Inst{47-40} = VDATA;
- let Inst{52-48} = SRSRC{6-2};
- let Inst{57-53} = SSAMP{6-2};
+ let Inst{39-32} = vaddr;
+ let Inst{47-40} = vdata;
+ let Inst{52-48} = srsrc{6-2};
+ let Inst{57-53} = ssamp{6-2};
}
class FLATe<bits<7> op> : Enc64 {
@@ -525,26 +507,26 @@ class FLATe<bits<7> op> : Enc64 {
}
class EXPe : Enc64 {
- bits<4> EN;
- bits<6> TGT;
- bits<1> COMPR;
- bits<1> DONE;
- bits<1> VM;
- bits<8> VSRC0;
- bits<8> VSRC1;
- bits<8> VSRC2;
- bits<8> VSRC3;
-
- let Inst{3-0} = EN;
- let Inst{9-4} = TGT;
- let Inst{10} = COMPR;
- let Inst{11} = DONE;
- let Inst{12} = VM;
+ bits<4> en;
+ bits<6> tgt;
+ bits<1> compr;
+ bits<1> done;
+ bits<1> vm;
+ bits<8> vsrc0;
+ bits<8> vsrc1;
+ bits<8> vsrc2;
+ bits<8> vsrc3;
+
+ let Inst{3-0} = en;
+ let Inst{9-4} = tgt;
+ let Inst{10} = compr;
+ let Inst{11} = done;
+ let Inst{12} = vm;
let Inst{31-26} = 0x3e;
- let Inst{39-32} = VSRC0;
- let Inst{47-40} = VSRC1;
- let Inst{55-48} = VSRC2;
- let Inst{63-56} = VSRC3;
+ let Inst{39-32} = vsrc0;
+ let Inst{47-40} = vsrc1;
+ let Inst{55-48} = vsrc2;
+ let Inst{63-56} = vsrc3;
}
let Uses = [EXEC] in {
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=229613&r1=229612&r2=229613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Tue Feb 17 20:15:35 2015
@@ -419,12 +419,12 @@ multiclass SOP1_64_0 <sop1 op, string op
def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
opName#" $dst"> {
- let SSRC0 = 0;
+ let ssrc0 = 0;
}
def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
opName#" $dst"> {
- let SSRC0 = 0;
+ let ssrc0 = 0;
}
}
@@ -1986,7 +1986,7 @@ class MIMG_NoSampler_Helper <bits<7> op,
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
#" $tfe, $lwe, $slc, $vaddr, $srsrc",
[]> {
- let SSAMP = 0;
+ let ssamp = 0;
let mayLoad = 1;
let mayStore = 0;
let hasPostISelHook = 1;
Modified: llvm/trunk/lib/Target/R600/VIInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/VIInstrFormats.td?rev=229613&r1=229612&r2=229613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/VIInstrFormats.td (original)
+++ llvm/trunk/lib/Target/R600/VIInstrFormats.td Tue Feb 17 20:15:35 2015
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
class DSe_vi <bits<8> op> : Enc64 {
-
bits<8> vdst;
bits<1> gds;
bits<8> addr;
@@ -33,7 +32,6 @@ class DSe_vi <bits<8> op> : Enc64 {
}
class MUBUFe_vi <bits<7> op> : Enc64 {
-
bits<12> offset;
bits<1> offen;
bits<1> idxen;
@@ -62,7 +60,6 @@ class MUBUFe_vi <bits<7> op> : Enc64 {
}
class MTBUFe_vi <bits<4> op> : Enc64 {
-
bits<12> offset;
bits<1> offen;
bits<1> idxen;
@@ -93,7 +90,6 @@ class MTBUFe_vi <bits<4> op> : Enc64 {
}
class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
-
bits<7> sbase;
bits<7> sdata;
bits<1> glc;
@@ -109,7 +105,6 @@ class SMEMe_vi <bits<8> op, bit imm> : E
}
class VOP3e_vi <bits<10> op> : Enc64 {
-
bits<8> dst;
bits<2> src0_modifiers;
bits<9> src0;
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