[PATCH] prevent folding a scalar FP load into a packed logical FP instruction (PR22371)

[Sanjay Patel]

In http://reviews.llvm.org/D7474#124867, @qcolombet wrote:

> Could you add tests for the new patterns?
>  I.e., some vector extract feeding an and.


Hi,

This goes back to my initial problem - I don't know how to generate the positive test cases:

1. We can't bitcast our way there via an integer logic op because those wouldn't be lowered to X86::F[AND,OR,XOR].
2. We can't coerce an fabs / fneg / fcopysign into this pattern because they load a scalar; fixing that would be my next patch on this path.

There's some hope / danger that we'll start generating more of these nodes for shuffles or if we fix this:
http://llvm.org/bugs/show_bug.cgi?id=22428

...but until then I don't know how to produce IR to match the pattern. Suggestions welcome. :)


http://reviews.llvm.org/D7474

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