[llvm] r228518 - ARM & AArch64: teach LowerVSETCC that output type size may differ from input.
hans at chromium.org
Sat Feb 7 18:00:33 PST 2015
On Sat, Feb 7, 2015 at 4:50 PM, Tim Northover <tnorthover at apple.com> wrote:
> Author: tnorthover
> Date: Sat Feb 7 18:50:47 2015
> New Revision: 228518
> URL: http://llvm.org/viewvc/llvm-project?rev=228518&view=rev
> ARM & AArch64: teach LowerVSETCC that output type size may differ from input.
> While various DAG combines try to guarantee that a vector SETCC
> operation will have the same output size as input, there's nothing
> intrinsic to either creation or LegalizeTypes that actually guarantees
> it, so the function needs to be ready to handle a mismatch.
> Fortunately this is easy enough, just extend or truncate the naturally
> compared result.
> I couldn't reproduce the failure in other backends that I know have
> SIMD, so it's probably only an issue for these two due to shared
> Should fix PR21645.
Is this suitable for merging to 3.6?
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