[llvm] r228228 - R600/SI: Enable subreg liveness by default
Alexey Samsonov
vonosmas at gmail.com
Thu Feb 5 13:00:34 PST 2015
+Matthias
Tom,
this change triggers a memory leak in subregister liveness analysis, and
breaks ASan bootstrap of LLVM:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/1319/steps/check-llvm%20asan/logs/stdio
The bug is in include/llvm/CodeGen/LiveInterval.h:
LiveInterval class contains a linked list of SubRange objects, which are
allocated with BumpPtrAllocator, and thus never deleted.
Each SubRange object contains a SmallVector<Segment, 4> of liveness
segments. Thus, if the number of segments during the analysis will exceed 4,
small vector will reallocate its storage with malloc(), and that storage
will never be deleted.
Matthias, you've added this code in r223877, any idea how to fix it?
Probably we could allocate SubRange objects with
SpecificBumpPtrAllocator<SubRange>,
but that won't work immediately, as the same BumpPtrAllocator is currently
re-used for allocating VNInfo.
On Wed, Feb 4, 2015 at 3:14 PM, Tom Stellard <thomas.stellard at amd.com>
wrote:
> Author: tstellar
> Date: Wed Feb 4 17:14:18 2015
> New Revision: 228228
>
> URL: http://llvm.org/viewvc/llvm-project?rev=228228&view=rev
> Log:
> R600/SI: Enable subreg liveness by default
>
> Modified:
> llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
> llvm/trunk/test/CodeGen/R600/imm.ll
> llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll
> llvm/trunk/test/CodeGen/R600/setcc-opt.ll
> llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h?rev=228228&r1=228227&r2=228228&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUSubtarget.h Wed Feb 4 17:14:18 2015
> @@ -243,6 +243,10 @@ public:
> // FIXME: Not sure what this is for other subtagets.
> llvm_unreachable("do not know max waves per CU for this subtarget.");
> }
> +
> + bool enableSubRegLiveness() const override {
> + return true;
> + }
> };
>
> } // End namespace llvm
>
> Modified: llvm/trunk/test/CodeGen/R600/imm.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/imm.ll?rev=228228&r1=228227&r2=228228&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/imm.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/imm.ll Wed Feb 4 17:14:18 2015
> @@ -24,7 +24,7 @@ entry:
>
> ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
> store float 0.0, float addrspace(1)* %out
> ret void
> @@ -32,7 +32,7 @@ define void @store_inline_imm_0.0_f32(fl
>
> ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
> store float -0.0, float addrspace(1)* %out
> ret void
> @@ -40,7 +40,7 @@ define void @store_imm_neg_0.0_f32(float
>
> ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
> store float 0.5, float addrspace(1)* %out
> ret void
> @@ -48,7 +48,7 @@ define void @store_inline_imm_0.5_f32(fl
>
> ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
> store float -0.5, float addrspace(1)* %out
> ret void
> @@ -56,7 +56,7 @@ define void @store_inline_imm_m_0.5_f32(
>
> ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
> store float 1.0, float addrspace(1)* %out
> ret void
> @@ -64,7 +64,7 @@ define void @store_inline_imm_1.0_f32(fl
>
> ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
> store float -1.0, float addrspace(1)* %out
> ret void
> @@ -72,7 +72,7 @@ define void @store_inline_imm_m_1.0_f32(
>
> ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
> store float 2.0, float addrspace(1)* %out
> ret void
> @@ -80,7 +80,7 @@ define void @store_inline_imm_2.0_f32(fl
>
> ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
> store float -2.0, float addrspace(1)* %out
> ret void
> @@ -88,7 +88,7 @@ define void @store_inline_imm_m_2.0_f32(
>
> ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
> store float 4.0, float addrspace(1)* %out
> ret void
> @@ -96,7 +96,7 @@ define void @store_inline_imm_4.0_f32(fl
>
> ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
> store float -4.0, float addrspace(1)* %out
> ret void
> @@ -104,7 +104,7 @@ define void @store_inline_imm_m_4.0_f32(
>
> ; CHECK-LABEL: {{^}}store_literal_imm_f32:
> ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @store_literal_imm_f32(float addrspace(1)* %out) {
> store float 4096.0, float addrspace(1)* %out
> ret void
> @@ -113,7 +113,7 @@ define void @store_literal_imm_f32(float
> ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0.0
> store float %y, float addrspace(1)* %out
> @@ -123,7 +123,7 @@ define void @add_inline_imm_0.0_f32(floa
> ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0.5
> store float %y, float addrspace(1)* %out
> @@ -133,7 +133,7 @@ define void @add_inline_imm_0.5_f32(floa
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float
> %x) {
> %y = fadd float %x, -0.5
> store float %y, float addrspace(1)* %out
> @@ -143,7 +143,7 @@ define void @add_inline_imm_neg_0.5_f32(
> ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 1.0
> store float %y, float addrspace(1)* %out
> @@ -153,7 +153,7 @@ define void @add_inline_imm_1.0_f32(floa
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float
> %x) {
> %y = fadd float %x, -1.0
> store float %y, float addrspace(1)* %out
> @@ -163,7 +163,7 @@ define void @add_inline_imm_neg_1.0_f32(
> ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 2.0
> store float %y, float addrspace(1)* %out
> @@ -173,7 +173,7 @@ define void @add_inline_imm_2.0_f32(floa
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float
> %x) {
> %y = fadd float %x, -2.0
> store float %y, float addrspace(1)* %out
> @@ -183,7 +183,7 @@ define void @add_inline_imm_neg_2.0_f32(
> ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 4.0
> store float %y, float addrspace(1)* %out
> @@ -193,7 +193,7 @@ define void @add_inline_imm_4.0_f32(floa
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float
> %x) {
> %y = fadd float %x, -4.0
> store float %y, float addrspace(1)* %out
> @@ -203,7 +203,7 @@ define void @add_inline_imm_neg_4.0_f32(
> ; CHECK-LABEL: @commute_add_inline_imm_0.5_f32
> ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
> ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out,
> float addrspace(1)* %in) {
> %x = load float addrspace(1)* %in
> %y = fadd float %x, 0.5
> @@ -214,7 +214,7 @@ define void @commute_add_inline_imm_0.5_
> ; CHECK-LABEL: @commute_add_literal_f32
> ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
> ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @commute_add_literal_f32(float addrspace(1)* %out, float
> addrspace(1)* %in) {
> %x = load float addrspace(1)* %in
> %y = fadd float %x, 1024.0
> @@ -225,7 +225,7 @@ define void @commute_add_literal_f32(flo
> ; CHECK-LABEL: {{^}}add_inline_imm_1_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0x36a0000000000000
> store float %y, float addrspace(1)* %out
> @@ -235,7 +235,7 @@ define void @add_inline_imm_1_f32(float
> ; CHECK-LABEL: {{^}}add_inline_imm_2_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0x36b0000000000000
> store float %y, float addrspace(1)* %out
> @@ -245,7 +245,7 @@ define void @add_inline_imm_2_f32(float
> ; CHECK-LABEL: {{^}}add_inline_imm_16_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0x36e0000000000000
> store float %y, float addrspace(1)* %out
> @@ -255,7 +255,7 @@ define void @add_inline_imm_16_f32(float
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x)
> {
> %y = fadd float %x, 0xffffffffe0000000
> store float %y, float addrspace(1)* %out
> @@ -265,7 +265,7 @@ define void @add_inline_imm_neg_1_f32(fl
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x)
> {
> %y = fadd float %x, 0xffffffffc0000000
> store float %y, float addrspace(1)* %out
> @@ -275,7 +275,7 @@ define void @add_inline_imm_neg_2_f32(fl
> ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float
> %x) {
> %y = fadd float %x, 0xfffffffe00000000
> store float %y, float addrspace(1)* %out
> @@ -285,7 +285,7 @@ define void @add_inline_imm_neg_16_f32(f
> ; CHECK-LABEL: {{^}}add_inline_imm_63_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0x36ff800000000000
> store float %y, float addrspace(1)* %out
> @@ -295,7 +295,7 @@ define void @add_inline_imm_63_f32(float
> ; CHECK-LABEL: {{^}}add_inline_imm_64_f32
> ; CHECK: s_load_dword [[VAL:s[0-9]+]]
> ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
> -; CHECK-NEXT: buffer_store_dword [[REG]]
> +; CHECK: buffer_store_dword [[REG]]
> define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
> %y = fadd float %x, 0x3700000000000000
> store float %y, float addrspace(1)* %out
>
> Modified: llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll?rev=228228&r1=228227&r2=228228&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/llvm.AMDGPU.class.ll Wed Feb 4 17:14:18
> 2015
> @@ -472,7 +472,7 @@ define void @test_no_fold_or_class_f32_0
> ; SI-LABEL: {{^}}test_class_0_f32:
> ; SI-NOT: v_cmp_class
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
> -; SI-NEXT: buffer_store_dword [[RESULT]]
> +; SI: buffer_store_dword [[RESULT]]
> ; SI: s_endpgm
> define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
> %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1
>
> Modified: llvm/trunk/test/CodeGen/R600/setcc-opt.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/setcc-opt.ll?rev=228228&r1=228227&r2=228228&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/setcc-opt.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/setcc-opt.ll Wed Feb 4 17:14:18 2015
> @@ -199,7 +199,7 @@ define void @cmp_sext_k_neg1_i8_arg(i1 a
>
> ; FUNC-LABEL: {{^}}cmp_zext_k_neg1:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> ; SI: s_endpgm
> define void @cmp_zext_k_neg1(i1 addrspace(1)* %out, i8 %b) nounwind {
> %b.ext = zext i8 %b to i32
> @@ -210,7 +210,7 @@ define void @cmp_zext_k_neg1(i1 addrspac
>
> ; FUNC-LABEL: {{^}}zext_bool_icmp_ne_k:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> ; SI-NEXT: s_endpgm
> define void @zext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b)
> nounwind {
> %icmp0 = icmp ne i32 %a, %b
> @@ -222,7 +222,7 @@ define void @zext_bool_icmp_ne_k(i1 addr
>
> ; FUNC-LABEL: {{^}}zext_bool_icmp_eq_k:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> ; SI-NEXT: s_endpgm
> define void @zext_bool_icmp_eq_k(i1 addrspace(1)* %out, i32 %a, i32 %b)
> nounwind {
> %icmp0 = icmp ne i32 %a, %b
>
> Modified: llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll?rev=228228&r1=228227&r2=228228&view=diff
>
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/trunc-cmp-constant.ll Wed Feb 4 17:14:18
> 2015
> @@ -34,7 +34,7 @@ define void @zextload_i1_to_i32_trunc_cm
>
> ; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_eq_1:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> define void @sextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1
> addrspace(1)* %in) nounwind {
> %load = load i1 addrspace(1)* %in
> %ext = sext i1 %load to i32
> @@ -69,7 +69,7 @@ define void @sextload_i1_to_i32_trunc_cm
>
> ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_eq_neg1:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> define void @zextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out,
> i1 addrspace(1)* %in) nounwind {
> %load = load i1 addrspace(1)* %in
> %ext = zext i1 %load to i32
> @@ -105,7 +105,7 @@ define void @zextload_i1_to_i32_trunc_cm
>
> ; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_ne_1:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> define void @sextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1
> addrspace(1)* %in) nounwind {
> %load = load i1 addrspace(1)* %in
> %ext = sext i1 %load to i32
> @@ -146,7 +146,7 @@ define void @sextload_i1_to_i32_trunc_cm
>
> ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_ne_neg1:
> ; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 1{{$}}
> -; SI-NEXT: buffer_store_byte [[RESULT]]
> +; SI: buffer_store_byte [[RESULT]]
> define void @zextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out,
> i1 addrspace(1)* %in) nounwind {
> %load = load i1 addrspace(1)* %in
> %ext = zext i1 %load to i32
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Alexey Samsonov
vonosmas at gmail.com
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