[PATCH] InstCombine: Transform select with and/or cond into select sequence

Matthias Braun matze at braunis.de
Wed Feb 4 17:45:30 PST 2015

I'm currently working on a new version that uses TLI->isOperationLegal(ISD::And, i1) / TLI->isOperationLegal(ISD::Or, i1) to decide whether to do the transform or not, is that sufficient for your targets?

- Matthias

> On Feb 4, 2015, at 5:41 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
> On 02/03/2015 08:14 PM, Matthias Braun wrote:
>> This transforms:
>> select((C0 & C1), a, b) -> select(C0, select(C1, a, b), b)
>> select((C0 | C1), a, b) -> select(C0, a, select(C1, a, b))
>> The result is better on most targets as C0 and C1 do not need to be
>> materialized into an integer register but can stay flags.
> I think this should be controllable by a target hook depending on the type. On R600, where a 64-bit select needs to be split into 2 instructions, this would be beneficial for 32-bit selects but not 64-bit (unless the select can be proven uniform in which case the second form is better for two reasons, but that's a much bigger problem to solve)
> -Matt
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

More information about the llvm-commits mailing list