[llvm] r227983 - Fix program crashes due to alignment exceptions generated for SSE memop instructions (PR22371).
Kuperstein, Michael M
michael.m.kuperstein at intel.com
Wed Feb 4 11:41:07 PST 2015
I understand this on roughly the same level as Nadav does (looks correct, and should be safer than the current situation), but Elena should be able to give an authoritative answer.
Elena, could you comment?
From: hwennborg at google.com [mailto:hwennborg at google.com] On Behalf Of Hans Wennborg
Sent: Wednesday, February 04, 2015 20:53
To: Nadav Rotem
Cc: Sanjay Patel; llvm-commits; Demikhovsky, Elena; Kuperstein, Michael M
Subject: Re: [llvm] r227983 - Fix program crashes due to alignment exceptions generated for SSE memop instructions (PR22371).
Elena, Michael: is this safe for merging to 3.6?
As far as I understand it's basically a revert or r224330.
On Tue, Feb 3, 2015 at 3:44 PM, Nadav Rotem <nrotem at apple.com> wrote:
> The change looks good to me, but I would wait a day and let Elena or
> Michael review it.
> On Feb 3, 2015, at 3:19 PM, Hans Wennborg <hans at chromium.org> wrote:
> On Tue, Feb 3, 2015 at 9:13 AM, Sanjay Patel <spatel at rotateright.com> wrote:
> Author: spatel
> Date: Tue Feb 3 11:13:04 2015
> New Revision: 227983
> URL: http://llvm.org/viewvc/llvm-project?rev=227983&view=rev
> Fix program crashes due to alignment exceptions generated for SSE
> memop instructions (PR22371).
> r224330 introduced a bug by misinterpreting the "FeatureVectorUAMem" bit.
> The commit log says that change did not affect anything, but that's
> not correct.
> That change allowed SSE instructions to have unaligned mem operands
> folded into math ops, and that's not allowed in the default
> specification for any SSE variant.
> The bug is exposed when compiling for an AVX-capable CPU that had this
> feature flag but without enabling AVX codegen. Another mistake in
> r224330 was not adding the feature flag to all AVX CPUs; the AMD chips
> were excluded.
> This is part of the fix for PR22371 (
> http://llvm.org/bugs/show_bug.cgi?id=22371 ).
> This feature bit is SSE-specific, so I've renamed it to
> Changed the existing test case for the feature bit to reflect the new
> name and renamed the test file itself to better reflect the feature.
> Added runs to fold-vex.ll to check for the failing codegen.
> Note that the feature bit is not set by default on any CPU because it
> may require a configuration register setting to enable the enhanced
> unaligned behavior.
> Sanjay requested in  that we should merge this to the 3.6 branch.
> I'm not qualified to determine if this is safe or not. Is there somone
> else with X86 expertise that would like to chime in? Nadav, you're
> listed as the code owner here.
> 1. http://llvm.org/bugs/show_bug.cgi?id=22374#c3
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