[llvm] r228124 - [x86] Start to introduce bit-masking based blend lowering.

[Aaron Ballman]

On Wed, Feb 4, 2015 at 4:06 AM, Chandler Carruth <chandlerc at gmail.com> wrote:
> Author: chandlerc
> Date: Wed Feb  4 03:06:05 2015
> New Revision: 228124
>
> URL: http://llvm.org/viewvc/llvm-project?rev=228124&view=rev
> Log:
> [x86] Start to introduce bit-masking based blend lowering.
>
> This is the simplest form of bit-math based blending which only fires
> when we are blending with zero and is relatively profitable. I've only
> enabled this path on very specific lowering strategies. I'm planning to
> widen its applicability in subsequent patches, but so far you'll notice
> that even though we get fewer shufps instructions, we *still* do the bit
> math in the FP execution port. I'm looking into why this is still
> happening.
>
> Modified:
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/X86/sse2.ll
>     llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll
>     llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=228124&r1=228123&r2=228124&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Feb  4 03:06:05 2015
> @@ -7733,6 +7733,46 @@ static SmallBitVector computeZeroableShu
>    return Zeroable;
>  }
>
> +/// \brief Try to emit a bitmask instruction for a shuffle.
> +///
> +/// This handles cases where we can model a blend exactly as a bitmask due to
> +/// one of the inputs being zeroable.
> +static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
> +                                           SDValue V2, ArrayRef<int> Mask,
> +                                           SelectionDAG &DAG) {
> +  MVT EltVT = VT.getScalarType();
> +  int NumEltBits = EltVT.getSizeInBits();
> +  MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
> +  SDValue Zero = DAG.getConstant(0, IntEltVT);
> +  SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
> +  if (EltVT.isFloatingPoint()) {
> +    Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
> +    AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
> +  }
> +  SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
> +  SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
> +  SDValue V;
> +  for (int i = 0, Size = Mask.size(); i < Size; ++i) {
> +    if (Zeroable[i])
> +      continue;
> +    if (Mask[i] % Size != i)
> +      return SDValue(); // Not a blend.
> +    if (!V)
> +      V = Mask[i] < Size ? V1 : V2;
> +    else if (V != (Mask[i] < Size ? V1 : V2))
> +      return SDValue(); // Can only let one input through the mask.
> +
> +    VMaskOps[i] = AllOnes;
> +  }
> +  if (!V)
> +    return SDValue(); // No non-zeroable elements!
> +
> +  SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
> +  V = DAG.getNode(VT.isFloatingPoint() ? X86ISD::FAND : ISD::AND, DL, VT, V,
> +                  VMask);

This is generating a warning, but I'm not particularly comfortable
with "fixing" it because I'm not entirely certain it's a problem.

X86ISelLowering.cpp: In function ‘llvm::SDValue
lowerVectorShuffleAsBitMask(llvm::SDLoc, llvm::MVT, llvm::SDValue,
llvm::SDValue, llvm::ArrayRef<int>, llvm::SelectionDAG&)’:
X86ISelLowering.cpp:7771:62: warning: enumeral mismatch in conditional
expression: ‘llvm::X86ISD::NodeType’ vs ‘llvm::ISD::NodeType’
[-Wenum-compare]

Can you silence this? Thanks!

~Aaron