[llvm] r228079 - Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.
Owen Anderson
resistor at mac.com
Tue Feb 3 16:02:59 PST 2015
Author: resistor
Date: Tue Feb 3 18:02:59 2015
New Revision: 228079
URL: http://llvm.org/viewvc/llvm-project?rev=228079&view=rev
Log:
Remove a gross usage of environment variables in MachineVerifier, replacing it with support for setting the -verify-machineinstrs flag via an environment variable in LIT.
This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications.
Modified:
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/lib/CodeGen/Passes.cpp
llvm/trunk/test/lit.cfg
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=228079&r1=228078&r2=228079&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Feb 3 18:02:59 2015
@@ -55,16 +55,13 @@ namespace {
MachineVerifier(Pass *pass, const char *b) :
PASS(pass),
- Banner(b),
- OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
+ Banner(b)
{}
bool runOnMachineFunction(MachineFunction &MF);
Pass *const PASS;
const char *Banner;
- const char *const OutFileName;
- raw_ostream *OS;
const MachineFunction *MF;
const TargetMachine *TM;
const TargetInstrInfo *TII;
@@ -277,22 +274,6 @@ void MachineFunction::verify(Pass *p, co
}
bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
- raw_ostream *OutFile = nullptr;
- if (OutFileName) {
- std::error_code EC;
- OutFile = new raw_fd_ostream(OutFileName, EC,
- sys::fs::F_Append | sys::fs::F_Text);
- if (EC) {
- errs() << "Error opening '" << OutFileName << "': " << EC.message()
- << '\n';
- exit(1);
- }
-
- OS = OutFile;
- } else {
- OS = &errs();
- }
-
foundErrors = 0;
this->MF = &MF;
@@ -327,7 +308,7 @@ bool MachineVerifier::runOnMachineFuncti
MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
if (MBBI->getParent() != MFI) {
report("Bad instruction parent pointer", MFI);
- *OS << "Instruction: " << *MBBI;
+ errs() << "Instruction: " << *MBBI;
continue;
}
@@ -363,9 +344,7 @@ bool MachineVerifier::runOnMachineFuncti
}
visitMachineFunctionAfter();
- if (OutFile)
- delete OutFile;
- else if (foundErrors)
+ if (foundErrors)
report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
// Clean up.
@@ -382,76 +361,76 @@ bool MachineVerifier::runOnMachineFuncti
void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
assert(MF);
- *OS << '\n';
+ errs() << '\n';
if (!foundErrors++) {
if (Banner)
- *OS << "# " << Banner << '\n';
- MF->print(*OS, Indexes);
+ errs() << "# " << Banner << '\n';
+ MF->print(errs(), Indexes);
}
- *OS << "*** Bad machine code: " << msg << " ***\n"
+ errs() << "*** Bad machine code: " << msg << " ***\n"
<< "- function: " << MF->getName() << "\n";
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
assert(MBB);
report(msg, MBB->getParent());
- *OS << "- basic block: BB#" << MBB->getNumber()
+ errs() << "- basic block: BB#" << MBB->getNumber()
<< ' ' << MBB->getName()
<< " (" << (const void*)MBB << ')';
if (Indexes)
- *OS << " [" << Indexes->getMBBStartIdx(MBB)
+ errs() << " [" << Indexes->getMBBStartIdx(MBB)
<< ';' << Indexes->getMBBEndIdx(MBB) << ')';
- *OS << '\n';
+ errs() << '\n';
}
void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
assert(MI);
report(msg, MI->getParent());
- *OS << "- instruction: ";
+ errs() << "- instruction: ";
if (Indexes && Indexes->hasIndex(MI))
- *OS << Indexes->getInstructionIndex(MI) << '\t';
- MI->print(*OS, TM);
+ errs() << Indexes->getInstructionIndex(MI) << '\t';
+ MI->print(errs(), TM);
}
void MachineVerifier::report(const char *msg,
const MachineOperand *MO, unsigned MONum) {
assert(MO);
report(msg, MO->getParent());
- *OS << "- operand " << MONum << ": ";
- MO->print(*OS, TM);
- *OS << "\n";
+ errs() << "- operand " << MONum << ": ";
+ MO->print(errs(), TM);
+ errs() << "\n";
}
void MachineVerifier::report(const char *msg, const MachineFunction *MF,
const LiveInterval &LI) {
report(msg, MF);
- *OS << "- interval: " << LI << '\n';
+ errs() << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
const LiveInterval &LI) {
report(msg, MBB);
- *OS << "- interval: " << LI << '\n';
+ errs() << "- interval: " << LI << '\n';
}
void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
const LiveRange &LR, unsigned Reg,
unsigned LaneMask) {
report(msg, MBB);
- *OS << "- liverange: " << LR << '\n';
- *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
+ errs() << "- liverange: " << LR << '\n';
+ errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
if (LaneMask != 0)
- *OS << "- lanemask: " << format("%04X\n", LaneMask);
+ errs() << "- lanemask: " << format("%04X\n", LaneMask);
}
void MachineVerifier::report(const char *msg, const MachineFunction *MF,
const LiveRange &LR, unsigned Reg,
unsigned LaneMask) {
report(msg, MF);
- *OS << "- liverange: " << LR << '\n';
- *OS << "- register: " << PrintReg(Reg, TRI) << '\n';
+ errs() << "- liverange: " << LR << '\n';
+ errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
if (LaneMask != 0)
- *OS << "- lanemask: " << format("%04X\n", LaneMask);
+ errs() << "- lanemask: " << format("%04X\n", LaneMask);
}
void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
@@ -539,7 +518,7 @@ MachineVerifier::visitMachineBasicBlockB
report("MBB has successor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
- *OS << "MBB is not in the predecessor list of the successor BB#"
+ errs() << "MBB is not in the predecessor list of the successor BB#"
<< (*I)->getNumber() << ".\n";
}
}
@@ -551,7 +530,7 @@ MachineVerifier::visitMachineBasicBlockB
report("MBB has predecessor that isn't part of the function.", MBB);
if (!MBBInfoMap[*I].Succs.count(MBB)) {
report("Inconsistent CFG", MBB);
- *OS << "MBB is not in the successor list of the predecessor BB#"
+ errs() << "MBB is not in the successor list of the predecessor BB#"
<< (*I)->getNumber() << ".\n";
}
}
@@ -726,7 +705,7 @@ void MachineVerifier::visitMachineBundle
SlotIndex idx = Indexes->getInstructionIndex(MI);
if (!(idx > lastIndex)) {
report("Instruction index out of order", MI);
- *OS << "Last instruction was at " << lastIndex << '\n';
+ errs() << "Last instruction was at " << lastIndex << '\n';
}
lastIndex = idx;
}
@@ -739,7 +718,7 @@ void MachineVerifier::visitMachineBundle
FirstTerminator = MI;
} else if (FirstTerminator) {
report("Non-terminator instruction after the first terminator", MI);
- *OS << "First terminator was:\t" << *FirstTerminator;
+ errs() << "First terminator was:\t" << *FirstTerminator;
}
}
@@ -791,7 +770,7 @@ void MachineVerifier::visitMachineInstrB
const MCInstrDesc &MCID = MI->getDesc();
if (MI->getNumOperands() < MCID.getNumOperands()) {
report("Too few operands", MI);
- *OS << MCID.getNumOperands() << " operands expected, but "
+ errs() << MCID.getNumOperands() << " operands expected, but "
<< MI->getNumOperands() << " given.\n";
}
@@ -921,7 +900,7 @@ MachineVerifier::visitMachineOperand(con
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (!DRC->contains(Reg)) {
report("Illegal physical register for instruction", MO, MONum);
- *OS << TRI->getName(Reg) << " is not a "
+ errs() << TRI->getName(Reg) << " is not a "
<< TRI->getRegClassName(DRC) << " register.\n";
}
}
@@ -933,13 +912,13 @@ MachineVerifier::visitMachineOperand(con
TRI->getSubClassWithSubReg(RC, SubIdx);
if (!SRC) {
report("Invalid subregister index for virtual register", MO, MONum);
- *OS << "Register class " << TRI->getRegClassName(RC)
+ errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not support subreg index " << SubIdx << "\n";
return;
}
if (RC != SRC) {
report("Invalid register class for subregister index", MO, MONum);
- *OS << "Register class " << TRI->getRegClassName(RC)
+ errs() << "Register class " << TRI->getRegClassName(RC)
<< " does not fully support subreg index " << SubIdx << "\n";
return;
}
@@ -961,7 +940,7 @@ MachineVerifier::visitMachineOperand(con
}
if (!RC->hasSuperClassEq(DRC)) {
report("Illegal virtual register for instruction", MO, MONum);
- *OS << "Expected a " << TRI->getRegClassName(DRC)
+ errs() << "Expected a " << TRI->getRegClassName(DRC)
<< " register, but got a " << TRI->getRegClassName(RC)
<< " register\n";
}
@@ -987,11 +966,11 @@ MachineVerifier::visitMachineOperand(con
SlotIndex Idx = LiveInts->getInstructionIndex(MI);
if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
report("Instruction loads from dead spill slot", MO, MONum);
- *OS << "Live stack: " << LI << '\n';
+ errs() << "Live stack: " << LI << '\n';
}
if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
report("Instruction stores to dead spill slot", MO, MONum);
- *OS << "Live stack: " << LI << '\n';
+ errs() << "Live stack: " << LI << '\n';
}
}
break;
@@ -1030,12 +1009,12 @@ void MachineVerifier::checkLiveness(cons
LiveQueryResult LRQ = LR->Query(UseIdx);
if (!LRQ.valueIn()) {
report("No live segment at use", MO, MONum);
- *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
+ errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
<< ' ' << *LR << '\n';
}
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
- *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
+ errs() << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
}
}
}
@@ -1048,13 +1027,13 @@ void MachineVerifier::checkLiveness(cons
LiveQueryResult LRQ = LI.Query(UseIdx);
if (!LRQ.valueIn()) {
report("No live segment at use", MO, MONum);
- *OS << UseIdx << " is not live in " << LI << '\n';
+ errs() << UseIdx << " is not live in " << LI << '\n';
}
// Check for extra kill flags.
// Note that we allow missing kill flags for now.
if (MO->isKill() && !LRQ.isKill()) {
report("Live range continues after kill flag", MO, MONum);
- *OS << "Live range: " << LI << '\n';
+ errs() << "Live range: " << LI << '\n';
}
} else {
report("Virtual register has no live interval", MO, MONum);
@@ -1137,19 +1116,19 @@ void MachineVerifier::checkLiveness(cons
assert(VNI && "NULL valno is not allowed");
if (VNI->def != DefIdx) {
report("Inconsistent valno->def", MO, MONum);
- *OS << "Valno " << VNI->id << " is not defined at "
+ errs() << "Valno " << VNI->id << " is not defined at "
<< DefIdx << " in " << LI << '\n';
}
} else {
report("No live segment at def", MO, MONum);
- *OS << DefIdx << " is not live in " << LI << '\n';
+ errs() << DefIdx << " is not live in " << LI << '\n';
}
// Check that, if the dead def flag is present, LiveInts agree.
if (MO->isDead()) {
LiveQueryResult LRQ = LI.Query(DefIdx);
if (!LRQ.isDeadDef()) {
report("Live range continues after dead def flag", MO, MONum);
- *OS << "Live range: " << LI << '\n';
+ errs() << "Live range: " << LI << '\n';
}
}
} else {
@@ -1191,7 +1170,7 @@ MachineVerifier::visitMachineBasicBlockA
SlotIndex stop = Indexes->getMBBEndIdx(MBB);
if (!(stop > lastIndex)) {
report("Block ends before last instruction index", MBB);
- *OS << "Block ends at " << stop
+ errs() << "Block ends at " << stop
<< " last instruction was at " << lastIndex << '\n';
}
lastIndex = stop;
@@ -1293,7 +1272,7 @@ void MachineVerifier::checkPHIOps(const
PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
if (!seen.count(*PrI)) {
report("Missing PHI operand", &BBI);
- *OS << "BB#" << (*PrI)->getNumber()
+ errs() << "BB#" << (*PrI)->getNumber()
<< " is a predecessor according to the CFG.\n";
}
}
@@ -1324,7 +1303,7 @@ void MachineVerifier::visitMachineFuncti
++I)
if (MInfo.regsKilled.count(*I)) {
report("Virtual register killed in block, but needed live out.", &MBB);
- *OS << "Virtual register " << PrintReg(*I)
+ errs() << "Virtual register " << PrintReg(*I)
<< " is used after the block.\n";
}
}
@@ -1356,13 +1335,13 @@ void MachineVerifier::verifyLiveVariable
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", &MBB);
- *OS << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << PrintReg(Reg)
<< " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MBB.getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", &MBB);
- *OS << "Virtual register " << PrintReg(Reg)
+ errs() << "Virtual register " << PrintReg(Reg)
<< " is not needed live through the block.\n";
}
}
@@ -1381,7 +1360,7 @@ void MachineVerifier::verifyLiveInterval
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
- *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
+ errs() << PrintReg(Reg, TRI) << " still has defs or uses\n";
continue;
}
@@ -1407,13 +1386,13 @@ void MachineVerifier::verifyLiveRangeVal
if (!DefVNI) {
report("Valno not live at def and not marked unused", MF, LR, Reg,
LaneMask);
- *OS << "Valno #" << VNI->id << '\n';
+ errs() << "Valno #" << VNI->id << '\n';
return;
}
if (DefVNI != VNI) {
report("Live segment at def has different valno", MF, LR, Reg, LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " where valno #" << DefVNI->id << " is live\n";
return;
}
@@ -1421,7 +1400,7 @@ void MachineVerifier::verifyLiveRangeVal
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
if (!MBB) {
report("Invalid definition index", MF, LR, Reg, LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LR << '\n';
return;
}
@@ -1430,7 +1409,7 @@ void MachineVerifier::verifyLiveRangeVal
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
report("PHIDef value is not defined at MBB start", MBB, LR, Reg,
LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def
<< ", not at the beginning of BB#" << MBB->getNumber() << '\n';
}
return;
@@ -1440,7 +1419,7 @@ void MachineVerifier::verifyLiveRangeVal
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
if (!MI) {
report("No instruction at def index", MBB, LR, Reg, LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
return;
}
@@ -1468,7 +1447,7 @@ void MachineVerifier::verifyLiveRangeVal
if (!hasDef) {
report("Defining instruction does not modify register", MI);
- *OS << "Valno #" << VNI->id << " in " << LR << '\n';
+ errs() << "Valno #" << VNI->id << " in " << LR << '\n';
}
// Early clobber defs begin at USE slots, but other defs must begin at
@@ -1477,12 +1456,12 @@ void MachineVerifier::verifyLiveRangeVal
if (!VNI->def.isEarlyClobber()) {
report("Early clobber def must be at an early-clobber slot", MBB, LR,
Reg, LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
}
} else if (!VNI->def.isRegister()) {
report("Non-PHI, non-early clobber def must be at a register slot",
MBB, LR, Reg, LaneMask);
- *OS << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
+ errs() << "Valno #" << VNI->id << " is defined at " << VNI->def << '\n';
}
}
}
@@ -1496,32 +1475,32 @@ void MachineVerifier::verifyLiveRangeSeg
if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
report("Foreign valno in live segment", MF, LR, Reg, LaneMask);
- *OS << S << " has a bad valno\n";
+ errs() << S << " has a bad valno\n";
}
if (VNI->isUnused()) {
report("Live segment valno is marked unused", MF, LR, Reg, LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
if (!MBB) {
report("Bad start of live segment, no basic block", MF, LR, Reg, LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
return;
}
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
if (S.start != MBBStartIdx && S.start != VNI->def) {
report("Live segment must begin at MBB entry or valno def", MBB, LR, Reg,
LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
}
const MachineBasicBlock *EndMBB =
LiveInts->getMBBFromIndex(S.end.getPrevSlot());
if (!EndMBB) {
report("Bad end of live segment, no basic block", MF, LR, Reg, LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
return;
}
@@ -1540,7 +1519,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!MI) {
report("Live segment doesn't end at a valid instruction", EndMBB, LR, Reg,
LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
return;
}
@@ -1548,7 +1527,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (S.end.isBlock()) {
report("Live segment ends at B slot of an instruction", EndMBB, LR, Reg,
LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
}
if (S.end.isDead()) {
@@ -1557,7 +1536,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!SlotIndex::isSameInstr(S.start, S.end)) {
report("Live segment ending at dead slot spans instructions", EndMBB, LR,
Reg, LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
}
}
@@ -1568,7 +1547,7 @@ void MachineVerifier::verifyLiveRangeSeg
report("Live segment ending at early clobber slot must be "
"redefined by an EC def in the same instruction", EndMBB, LR, Reg,
LaneMask);
- *OS << S << '\n';
+ errs() << S << '\n';
}
}
@@ -1597,7 +1576,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!MRI->tracksSubRegLiveness() || LaneMask != 0 || !hasSubRegDef) {
report("Instruction ending live segment doesn't read the register",
MI);
- *OS << S << " in " << LR << '\n';
+ errs() << S << " in " << LR << '\n';
}
}
}
@@ -1638,7 +1617,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!PVNI) {
report("Register not marked live out of predecessor", *PI, LR, Reg,
LaneMask);
- *OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
+ errs() << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
<< PEnd << '\n';
continue;
@@ -1648,7 +1627,7 @@ void MachineVerifier::verifyLiveRangeSeg
if (!IsPHI && PVNI != VNI) {
report("Different value live out of predecessor", *PI, LR, Reg,
LaneMask);
- *OS << "Valno #" << PVNI->id << " live out of BB#"
+ errs() << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << '\n';
@@ -1697,12 +1676,12 @@ void MachineVerifier::verifyLiveInterval
if (NumComp > 1) {
report("Multiple connected components in live interval", MF, LI);
for (unsigned comp = 0; comp != NumComp; ++comp) {
- *OS << comp << ": valnos";
+ errs() << comp << ": valnos";
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
E = LI.vni_end(); I!=E; ++I)
if (comp == ConEQ.getEqClass(*I))
- *OS << ' ' << (*I)->id;
- *OS << '\n';
+ errs() << ' ' << (*I)->id;
+ errs() << '\n';
}
}
}
@@ -1783,7 +1762,7 @@ void MachineVerifier::verifyStackFrame()
BBState.ExitValue;
if (BBState.ExitIsSetup && AbsSPAdj != Size) {
report("FrameDestroy <n> is after FrameSetup <m>", &I);
- *OS << "FrameDestroy <" << Size << "> is after FrameSetup <"
+ errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
<< AbsSPAdj << ">.\n";
}
BBState.ExitValue += Size;
@@ -1800,7 +1779,7 @@ void MachineVerifier::verifyStackFrame()
(SPState[(*I)->getNumber()].ExitValue != BBState.EntryValue ||
SPState[(*I)->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
report("The exit stack state of a predecessor is inconsistent.", MBB);
- *OS << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
+ errs() << "Predecessor BB#" << (*I)->getNumber() << " has exit state ("
<< SPState[(*I)->getNumber()].ExitValue << ", "
<< SPState[(*I)->getNumber()].ExitIsSetup
<< "), while BB#" << MBB->getNumber() << " has entry state ("
@@ -1816,7 +1795,7 @@ void MachineVerifier::verifyStackFrame()
(SPState[(*I)->getNumber()].EntryValue != BBState.ExitValue ||
SPState[(*I)->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
report("The entry stack state of a successor is inconsistent.", MBB);
- *OS << "Successor BB#" << (*I)->getNumber() << " has entry state ("
+ errs() << "Successor BB#" << (*I)->getNumber() << " has entry state ("
<< SPState[(*I)->getNumber()].EntryValue << ", "
<< SPState[(*I)->getNumber()].EntryIsSetup
<< "), while BB#" << MBB->getNumber() << " has exit state ("
Modified: llvm/trunk/lib/CodeGen/Passes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/Passes.cpp?rev=228079&r1=228078&r2=228079&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/Passes.cpp (original)
+++ llvm/trunk/lib/CodeGen/Passes.cpp Tue Feb 3 18:02:59 2015
@@ -81,7 +81,9 @@ static cl::opt<bool> PrintGCInfo("print-
cl::desc("Dump garbage collector data"));
static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
cl::desc("Verify generated machine code"),
- cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=nullptr));
+ cl::init(false),
+ cl::ZeroOrMore);
+
static cl::opt<std::string>
PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
cl::desc("Print machine instrs"),
Modified: llvm/trunk/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=228079&r1=228078&r2=228079&view=diff
==============================================================================
--- llvm/trunk/test/lit.cfg (original)
+++ llvm/trunk/test/lit.cfg Tue Feb 3 18:02:59 2015
@@ -270,6 +270,10 @@ for pattern in [r"\bbugpoint\b(?!-)",
# Warn, but still provide a substitution.
lit_config.note('Did not find ' + tool_name + ' in ' + llvm_tools_dir)
tool_path = llvm_tools_dir + '/' + tool_name
+ if (tool_name == "llc" and
+ 'LLVM_ENABLE_MACHINE_VERIFIER' in os.environ and
+ os.environ['LLVM_ENABLE_MACHINE_VERIFIER'] == "1"):
+ tool_path += " -verify-machineinstrs"
config.substitutions.append((pattern, tool_pipe + tool_path))
### Targets
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