[llvm] r228019 - [Hexagon] Updating XTYPE/PRED intrinsics.
Colin LeMahieu
colinl at codeaurora.org
Tue Feb 3 11:43:59 PST 2015
Author: colinl
Date: Tue Feb 3 13:43:59 2015
New Revision: 228019
URL: http://llvm.org/viewvc/llvm-project?rev=228019&view=rev
Log:
[Hexagon] Updating XTYPE/PRED intrinsics.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td
llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td?rev=228019&r1=228018&r2=228019&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsics.td Tue Feb 3 13:43:59 2015
@@ -1090,6 +1090,25 @@ def : T_P_pat <S2_vsatwh_nopack, int_hex
def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
/********************************************************************
+* STYPE/PRED *
+*********************************************************************/
+
+// Predicate transfer
+def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))),
+ (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
+def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))),
+ (i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
+
+// Mask generate from predicate
+def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))),
+ (i64 (C2_mask (C2_tfrrp (I32:$Rs))))>;
+
+// Viterbi pack even and odd predicate bits
+def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))),
+ (i32 (C2_vitpack (C2_tfrrp (I32:$Rs)),
+ (C2_tfrrp (I32:$Rt))))>;
+
+/********************************************************************
* STYPE/SHIFT *
*********************************************************************/
@@ -1705,25 +1724,6 @@ class di_LDInstPI_diu4<string opc, Intri
"$src1 = $dst">;
/********************************************************************
-* STYPE/PRED *
-*********************************************************************/
-
-// STYPE / PRED / Mask generate from predicate.
-def HEXAGON_C2_mask:
- di_SInst_qi <"mask", int_hexagon_C2_mask>;
-
-// STYPE / PRED / Predicate transfer.
-def HEXAGON_C2_tfrpr:
- si_SInst_qi <"", int_hexagon_C2_tfrpr>;
-def HEXAGON_C2_tfrrp:
- qi_SInst_si <"", int_hexagon_C2_tfrrp>;
-
-// STYPE / PRED / Viterbi pack even and odd predicate bits.
-def HEXAGON_C2_vitpack:
- si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
-
-
-/********************************************************************
* STYPE/VH *
*********************************************************************/
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td?rev=228019&r1=228018&r2=228019&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIntrinsicsV4.td Tue Feb 3 13:43:59 2015
@@ -78,6 +78,25 @@ def: T_RR_pat<C4_nbitsset, int_hexagon_
def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
+
+class vcmpImm_pat <InstHexagon MI, Intrinsic IntID, PatLeaf immPred> :
+ Pat <(IntID (i64 DoubleRegs:$src1), immPred:$src2),
+ (MI (i64 DoubleRegs:$src1), immPred:$src2)>;
+
+def : vcmpImm_pat <A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi, u8ImmPred>;
+def : vcmpImm_pat <A4_vcmpbgti, int_hexagon_A4_vcmpbgti, s8ImmPred>;
+def : vcmpImm_pat <A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui, u7ImmPred>;
+
+def : vcmpImm_pat <A4_vcmpheqi, int_hexagon_A4_vcmpheqi, s8ImmPred>;
+def : vcmpImm_pat <A4_vcmphgti, int_hexagon_A4_vcmphgti, s8ImmPred>;
+def : vcmpImm_pat <A4_vcmphgtui, int_hexagon_A4_vcmphgtui, u7ImmPred>;
+
+def : vcmpImm_pat <A4_vcmpweqi, int_hexagon_A4_vcmpweqi, s8ImmPred>;
+def : vcmpImm_pat <A4_vcmpwgti, int_hexagon_A4_vcmpwgti, s8ImmPred>;
+def : vcmpImm_pat <A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui, u7ImmPred>;
+
+def : T_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>;
+
def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
Modified: llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll?rev=228019&r1=228018&r2=228019&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/intrinsics/xtype_pred.ll Tue Feb 3 13:43:59 2015
@@ -158,7 +158,7 @@ define i64 @C2_mask(i32 %a) {
%z = call i64 @llvm.hexagon.C2.mask(i32 %a)
ret i64 %z
}
-; CHECK: = mask(r0)
+; CHECK: = mask(p0)
; Check for TLB match
declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32)
@@ -196,3 +196,156 @@ define i32 @S4_ntstbit_r(i32 %a, i32 %b)
ret i32 %z
}
; CHECK: p0 = !tstbit(r0, r1)
+
+; Vector compare halfwords
+declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64)
+define i32 @A2_vcmpheq(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64)
+define i32 @A2_vcmphgt(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64)
+define i32 @A2_vcmphgtu(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32)
+define i32 @A4_vcmpheqi(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32)
+define i32 @A4_vcmphgti(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32)
+define i32 @A4_vcmphgtui(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmph.gtu(r1:0, #0)
+
+; Vector compare bytes for any match
+declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64)
+define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
+
+; Vector compare bytes
+declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64)
+define i32 @A2_vcmpbeq(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64)
+define i32 @A2_vcmpbgtu(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64)
+define i32 @A4_vcmpbgt(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32)
+define i32 @A4_vcmpbeqi(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32)
+define i32 @A4_vcmpbgti(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32)
+define i32 @A4_vcmpbgtui(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpb.gtu(r1:0, #0)
+
+; Vector compare words
+declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64)
+define i32 @A2_vcmpweq(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.eq(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64)
+define i32 @A2_vcmpwgt(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.gt(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64)
+define i32 @A2_vcmpwgtu(i64 %a, i64 %b) {
+ %z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.gtu(r1:0, r3:2)
+
+declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32)
+define i32 @A4_vcmpweqi(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.eq(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32)
+define i32 @A4_vcmpwgti(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.gt(r1:0, #0)
+
+declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32)
+define i32 @A4_vcmpwgtui(i64 %a) {
+ %z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0)
+ ret i32 %z
+}
+; CHECK: p0 = vcmpw.gtu(r1:0, #0)
+
+; Viterbi pack even and odd predicate bitsclr
+declare i32 @llvm.hexagon.C2.vitpack(i32, i32)
+define i32 @C2_vitpack(i32 %a, i32 %b) {
+ %z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b)
+ ret i32 %z
+}
+; CHECK: r0 = vitpack(p1, p0)
+
+; Vector mux
+declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64)
+define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) {
+ %z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c)
+ ret i64 %z
+}
+; CHECK: = vmux(p0, r3:2, r5:4)
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