[PATCH] [AArch64] Fix problems in handling generic MSR/MRS instructions
petr.pavlu at arm.com
Mon Jan 26 03:29:31 PST 2015
This change fixes the following problems:
1) Decoding to MSRpstate should occur only if <op1><op2> represents a valid <pstatefield>, else the instruction should be decoded to a generic MSR.
2) AsmParser should not produce a MSR/MRS MCInst that can encode to a same bitpattern as another system instruction.
Unfortunately, it seems it is currently not possible to fix these problems cleanly at the TableGen level. The patch works around it by ugly rewriting MCInsts in Disassembler and AsmParser.
-------------- next part --------------
A non-text attachment was scrubbed...
Size: 11768 bytes
Desc: not available
More information about the llvm-commits