[llvm] r226816 - [DAGCombine] Produce better code for constant splats
Andrea Di Biagio
andrea.dibiagio at gmail.com
Sat Jan 24 03:57:41 PST 2015
Hi Patrik,
thanks for reporting this bug.
I fixed this regression at revision 227002.
Cheers,
Andrea
On Fri, Jan 23, 2015 at 7:39 PM, Patrik Hägglund H
<patrik.h.hagglund at ericsson.com> wrote:
> Hi Michael,
>
> This commit caused a regression found with 'bin/llvm-stress -size 240 -seed 26299 | bin/llc -march=x86-64 -mcpu=corei7 -o /dev/null'.
>
> llc: ../lib/CodeGen/SelectionDAG/SelectionDAG.cpp:738: void VerifySDNode(llvm::SDNode *): Assertion `N->getNumOperands() == N->getValueType(0).getVectorNumElements() && "Wrong number of operands!"' failed.
>
> Here is a bugpoint-simplified version:
>
> ; ModuleID = 'bugpoint-reduced-simplified.bc'
> target triple = "x86_64-unknown-linux-gnu"
>
> define void @autogen_SD26299(i8) {
> BB:
> %Shuff = shufflevector <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> zeroinitializer, <8 x i32> <i32 2, i32 undef, i32 6, i32 8, i32 undef, i32 12, i32 14, i32 0>
> %Shuff14 = shufflevector <8 x i32> %Shuff, <8 x i32> %Shuff, <8 x i32> <i32 7, i32 9, i32 11, i32 undef, i32 undef, i32 1, i32 3, i32 5>
> %Shuff35 = shufflevector <8 x i32> %Shuff14, <8 x i32> %Shuff, <8 x i32> <i32 undef, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13>
> %I42 = insertelement <8 x i32> %Shuff35, i32 88608, i32 0
> %Shuff48 = shufflevector <8 x i32> %Shuff35, <8 x i32> %I42, <8 x i32> <i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2>
> %Tr59 = trunc <8 x i32> %Shuff48 to <8 x i8>
> br label %CF
>
> CF: ; preds = %CF196, %CF, %BB
> br i1 undef, label %CF, label %CF196
>
> CF196: ; preds = %CF
> %I65 = insertelement <8 x i8> %Tr59, i8 %0, i32 4
> br label %CF
> }
>
> /Patrik Hägglund
>
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Michael Kuperstein
> Sent: den 22 januari 2015 14:07
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm] r226816 - [DAGCombine] Produce better code for constant splats
>
> Author: mkuper
> Date: Thu Jan 22 07:07:28 2015
> New Revision: 226816
>
> URL: http://llvm.org/viewvc/llvm-project?rev=226816&view=rev
> Log:
> [DAGCombine] Produce better code for constant splats
>
> This solves PR22276.
> Splats of constants would sometimes produce redundant shuffles, sometimes ridiculously so (see the PR for details). Fold these shuffles into BUILD_VECTORs early on instead.
>
> Differential Revision: http://reviews.llvm.org/D7093
>
> Fixed recommit of r226811.
>
> Added:
> llvm/trunk/test/CodeGen/X86/splat-const.ll
> - copied unchanged from r226813, llvm/trunk/test/CodeGen/X86/splat-const.ll
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> llvm/trunk/test/CodeGen/X86/sse41.ll
> llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=226816&r1=226815&r2=226816&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 22 07:07:28 2015
> @@ -11490,7 +11490,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE
> }
>
> // If it is a splat, check if the argument vector is another splat or a
> - // build_vector with all scalar elements the same.
> + // build_vector.
> if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
> SDNode *V = N0.getNode();
>
> @@ -11527,6 +11527,24 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE
> // Splat of <x, x, x, x>, return <x, x, x, x>
> if (AllSame)
> return N0;
> +
> + // If the splatted element is a constant, just build the vector out of
> + // constants directly.
> + const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
> + if (isa<ConstantSDNode>(Splatted) || isa<ConstantFPSDNode>(Splatted)) {
> + SmallVector<SDValue, 8> Ops;
> + for (unsigned i = 0; i != NumElts; ++i) {
> + Ops.push_back(Splatted);
> + }
> + SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
> + V->getValueType(0), Ops);
> +
> + // We may have jumped through bitcasts, so the type of the
> + // BUILD_VECTOR may not match the type of the shuffle.
> + if (V->getValueType(0) != VT)
> + NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
> + return NewBV;
> + }
> }
> }
>
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=226816&r1=226815&r2=226816&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jan 22 07:07:28 2015
> @@ -1513,9 +1513,10 @@ SDValue SelectionDAG::getVectorShuffle(E
> return getUNDEF(VT);
>
> // If Identity shuffle return that node.
> - bool Identity = true;
> + bool Identity = true, AllSame = true;
> for (unsigned i = 0; i != NElts; ++i) {
> if (MaskVec[i] >= 0 && MaskVec[i] != (int)i) Identity = false;
> + if (MaskVec[i] != MaskVec[0]) AllSame = false;
> }
> if (Identity && NElts)
> return N1;
> @@ -1549,6 +1550,26 @@ SDValue SelectionDAG::getVectorShuffle(E
> if (C->isNullValue())
> return N1;
> }
> +
> + // If the shuffle itself creates a constant splat, build the vector
> + // directly.
> + if (AllSame) {
> + const SDValue &Splatted = BV->getOperand(MaskVec[0]);
> + if (isa<ConstantSDNode>(Splatted) || isa<ConstantFPSDNode>(Splatted)) {
> + SmallVector<SDValue, 8> Ops;
> + for (unsigned i = 0; i != NElts; ++i) {
> + Ops.push_back(Splatted);
> + }
> + SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl,
> + BV->getValueType(0), Ops);
> +
> + // We may have jumped through bitcasts, so the type of the
> + // BUILD_VECTOR may not match the type of the shuffle.
> + if (BV->getValueType(0) != VT)
> + NewBV = getNode(ISD::BITCAST, dl, VT, NewBV);
> + return NewBV;
> + }
> + }
> }
> }
>
>
> Modified: llvm/trunk/test/CodeGen/X86/sse41.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse41.ll?rev=226816&r1=226815&r2=226816&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/sse41.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/sse41.ll Thu Jan 22 07:07:28 2015
> @@ -1003,14 +1003,14 @@ define void @insertps_pr20411(i32* noali
> ; X32-LABEL: insertps_pr20411:
> ; X32: ## BB#0:
> ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
> -; X32-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
> +; X32-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3]
> ; X32-NEXT: insertps $-36, LCPI49_1+12, %xmm0
> ; X32-NEXT: movups %xmm0, (%eax)
> ; X32-NEXT: retl
> ;
> ; X64-LABEL: insertps_pr20411:
> ; X64: ## BB#0:
> -; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
> +; X64-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3]
> ; X64-NEXT: insertps $-36, LCPI49_1+{{.*}}(%rip), %xmm0
> ; X64-NEXT: movups %xmm0, (%rdi)
> ; X64-NEXT: retq
>
> Modified: llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll?rev=226816&r1=226815&r2=226816&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/widen_shuffle-1.ll Thu Jan 22 07:07:28 2015
> @@ -82,8 +82,8 @@ define void @shuf5(<8 x i8>* %p) nounwin
> ; CHECK-LABEL: shuf5:
> ; CHECK: # BB#0:
> ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
> -; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <4,33,u,u,u,u,u,u>
> -; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
> +; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [33,33,33,33,33,33,33,33]
> +; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u]
> ; CHECK-NEXT: movlpd %xmm0, (%eax)
> ; CHECK-NEXT: retl
> %v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
>
>
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