[llvm] r226806 - Fixed a comment
Elena Demikhovsky
elena.demikhovsky at intel.com
Thu Jan 22 02:01:36 PST 2015
Author: delena
Date: Thu Jan 22 04:01:36 2015
New Revision: 226806
URL: http://llvm.org/viewvc/llvm-project?rev=226806&view=rev
Log:
Fixed a comment
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=226806&r1=226805&r2=226806&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jan 22 04:01:36 2015
@@ -9497,7 +9497,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWi
unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
unsigned NewBW = NextPowerOf2(MSB - ShAmt);
EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
- // The narowwing should be profitable, the load/store operation should be
+ // The narrowwing should be profitable, the load/store operation should be
// legal (or custom) and the store size should be equal to the NewVT width.
while (NewBW < BitWidth &&
(NewVT.getStoreSizeInBits() != NewBW ||
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