[llvm] r226665 - Revert "DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))"
Tim Northover
tnorthover at apple.com
Wed Jan 21 07:48:53 PST 2015
Author: tnorthover
Date: Wed Jan 21 09:48:52 2015
New Revision: 226665
URL: http://llvm.org/viewvc/llvm-project?rev=226665&view=rev
Log:
Revert "DAGCombine: fold (or (and X, M), (and X, N)) -> (and X, (or M, N))"
It hadn't gone through review yet, but was still on my local copy.
This reverts commit r226663
Removed:
llvm/trunk/test/CodeGen/AArch64/or-combine.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/R600/extload.ll
llvm/trunk/test/CodeGen/X86/vselect.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=226665&r1=226664&r2=226665&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 21 09:48:52 2015
@@ -3527,17 +3527,6 @@ SDValue DAGCombiner::visitOR(SDNode *N)
}
}
- // (or (and X, M), (and X, N)) -> (and X, (or M, N))
- if (N0.getOpcode() == ISD::AND &&
- N1.getOpcode() == ISD::AND &&
- N0.getOperand(0) == N1.getOperand(0) &&
- // Don't increase # computations.
- (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
- SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
- N0.getOperand(1), N1.getOperand(1));
- return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0), X);
- }
-
// See if this is some rotate idiom.
if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
return SDValue(Rot, 0);
Removed: llvm/trunk/test/CodeGen/AArch64/or-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/or-combine.ll?rev=226664&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/or-combine.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/or-combine.ll (removed)
@@ -1,44 +0,0 @@
-; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
-
-define i32 @test_consts(i32 %in) {
-; CHECK-LABEL: test_consts:
-; CHECK-NOT: bfxil
-; CHECK-NOT: and
-; CHECK-NOT: orr
-; CHECK: ret
-
- %lo = and i32 %in, 65535
- %hi = and i32 %in, -65536
- %res = or i32 %lo, %hi
- ret i32 %res
-}
-
-define i32 @test_generic(i32 %in, i32 %mask1, i32 %mask2) {
-; CHECK-LABEL: test_generic:
-; CHECK: orr [[FULL_MASK:w[0-9]+]], w1, w2
-; CHECK: and w0, w0, [[FULL_MASK]]
-
- %lo = and i32 %in, %mask1
- %hi = and i32 %in, %mask2
- %res = or i32 %lo, %hi
- ret i32 %res
-}
-
-; In this case the transformation isn't profitable, since %lo and %hi
-; are used more than once.
-define [3 x i32] @test_reuse(i32 %in, i32 %mask1, i32 %mask2) {
-; CHECK-LABEL: test_reuse:
-; CHECK-DAG: and w1, w0, w1
-; CHECK-DAG: and w2, w0, w2
-; CHECK-DAG: orr w0, w1, w2
-
- %lo = and i32 %in, %mask1
- %hi = and i32 %in, %mask2
- %recombine = or i32 %lo, %hi
-
- %res.tmp0 = insertvalue [3 x i32] undef, i32 %recombine, 0
- %res.tmp1 = insertvalue [3 x i32] %res.tmp0, i32 %lo, 1
- %res = insertvalue [3 x i32] %res.tmp1, i32 %hi, 2
-
- ret [3 x i32] %res
-}
Modified: llvm/trunk/test/CodeGen/R600/extload.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/extload.ll?rev=226665&r1=226664&r2=226665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/R600/extload.ll (original)
+++ llvm/trunk/test/CodeGen/R600/extload.ll Wed Jan 21 09:48:52 2015
@@ -2,9 +2,8 @@
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}anyext_load_i8:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
-; EG: VTX_READ_32 [[VAL]]
-
+; EG: AND_INT
+; EG: 255
define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind {
%cast = bitcast i8 addrspace(1)* %src to i32 addrspace(1)*
%load = load i32 addrspace(1)* %cast, align 1
@@ -15,9 +14,10 @@ define void @anyext_load_i8(i8 addrspace
}
; FUNC-LABEL: {{^}}anyext_load_i16:
-; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]],
-; EG: VTX_READ_32 [[VAL]]
-
+; EG: AND_INT
+; EG: AND_INT
+; EG-DAG: 65535
+; EG-DAG: -65536
define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind {
%cast = bitcast i16 addrspace(1)* %src to i32 addrspace(1)*
%load = load i32 addrspace(1)* %cast, align 1
@@ -28,8 +28,8 @@ define void @anyext_load_i16(i16 addrspa
}
; FUNC-LABEL: {{^}}anyext_load_lds_i8:
-; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
-; EG: LDS_WRITE * [[VAL]]
+; EG: AND_INT
+; EG: 255
define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind {
%cast = bitcast i8 addrspace(3)* %src to i32 addrspace(3)*
%load = load i32 addrspace(3)* %cast, align 1
@@ -40,8 +40,10 @@ define void @anyext_load_lds_i8(i8 addrs
}
; FUNC-LABEL: {{^}}anyext_load_lds_i16:
-; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]]
-; EG: LDS_WRITE * [[VAL]]
+; EG: AND_INT
+; EG: AND_INT
+; EG-DAG: 65535
+; EG-DAG: -65536
define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind {
%cast = bitcast i16 addrspace(3)* %src to i32 addrspace(3)*
%load = load i32 addrspace(3)* %cast, align 1
Modified: llvm/trunk/test/CodeGen/X86/vselect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vselect.ll?rev=226665&r1=226664&r2=226665&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vselect.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vselect.ll Wed Jan 21 09:48:52 2015
@@ -53,9 +53,10 @@ define <4 x float> @test5(<4 x float> %a
define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test6:
; CHECK: # BB#0:
-; CHECK-NEXT: movaps {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0]
-; CHECK-NEXT: orps {{.*}}(%rip), %xmm1
-; CHECK-NEXT: andps %xmm1, %xmm0
+; CHECK-NEXT: movaps {{.*#+}} xmm1 = [0,65535,0,65535,0,65535,0,65535]
+; CHECK-NEXT: andps %xmm0, %xmm1
+; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
+; CHECK-NEXT: orps %xmm1, %xmm0
; CHECK-NEXT: retq
%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
ret <8 x i16> %1
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