[PATCH] [ARM] Fix SMLAL (Signed Multiply Accumulate Long) lowering

[Jyoti Allur]

Hi t.p.northover, compnerd,

[ARM] This patch addresses following issue.

long long foo(int a, int b, int c, int d) {
  long long acc = (long long)a * (long long)b;
  acc += (long long)c * (long long)d;
  return acc;
}

Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
two signed 32-bit values to produce a 64-bit value, and accumulates this with
a 64-bit value.

We currently get this for v7:

_foo:
        smull	 r0, r1, r1, r0
	smull	 r2, r3, r3, r2
	adds	r0, r2, r0
	adc	r1, r3, r1
	bx	lr

The above is reduced to following with this patch:

_foo:
        smull	 r0, r1, r1, r0
	smlal	 r0, r1, r3, r2
	bx	lr

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6998

Files:
  ../llvm/lib/Target/ARM/ARMISelLowering.cpp
  ../llvm/test/CodeGen/ARM/longMAC.ll

Index: ../llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- ../llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ ../llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8075,12 +8075,14 @@
   else
     HiAdd = &AddeOp0;
 
+  // When both operands of ADDC are a result from different ISD::SMUL_LOHI,
+  // prevent LoMul from being overwritten with first ISD::SMUL_LOHI result.
 
   if (AddcOp0->getOpcode() == Opc) {
     LoMul = &AddcOp0;
     LowAdd = &AddcOp1;
   }
-  if (AddcOp1->getOpcode() == Opc) {
+  else if (AddcOp1->getOpcode() == Opc) {
     LoMul = &AddcOp1;
     LowAdd = &AddcOp0;
   }
Index: ../llvm/test/CodeGen/ARM/longMAC.ll
===================================================================
--- ../llvm/test/CodeGen/ARM/longMAC.ll
+++ ../llvm/test/CodeGen/ARM/longMAC.ll
@@ -75,3 +75,17 @@
   %add = add i64 %mul, %c
   ret i64 %add
 }
+
+define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
+;CHECK-LABEL: MACLongTest6:
+;CHECK: smlal
+  %conv = sext i32 %a to i64
+  %conv1 = sext i32 %b to i64
+  %mul = mul nsw i64 %conv1, %conv
+  %conv2 = sext i32 %c to i64
+  %conv3 = sext i32 %d to i64
+  %mul4 = mul nsw i64 %conv3, %conv2
+  %add = add nsw i64 %mul4, %mul
+  ret i64 %add
+}
+

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