[llvm] r226065 - [Hexagon] Replacing old versions of stores and loads.
Colin LeMahieu
colinl at codeaurora.org
Wed Jan 14 16:15:30 PST 2015
Author: colinl
Date: Wed Jan 14 18:15:30 2015
New Revision: 226065
URL: http://llvm.org/viewvc/llvm-project?rev=226065&view=rev
Log:
[Hexagon] Replacing old versions of stores and loads.
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=226065&r1=226064&r2=226065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Jan 14 18:15:30 2015
@@ -770,14 +770,6 @@ getMatchingCondBranchOpcode(int Opc, boo
return !invertPredicate ? Hexagon::C2_ccombinewt :
Hexagon::C2_ccombinewf;
- // Word.
- case Hexagon::STriw_f:
- return !invertPredicate ? Hexagon::S2_pstorerit_io:
- Hexagon::S2_pstorerif_io;
- case Hexagon::STriw_indexed_f:
- return !invertPredicate ? Hexagon::S2_pstorerit_io:
- Hexagon::S2_pstorerif_io;
-
// DEALLOC_RETURN.
case Hexagon::L4_return:
return !invertPredicate ? Hexagon::L4_return_t:
@@ -1094,15 +1086,12 @@ isValidOffset(const int Opcode, const in
switch(Opcode) {
case Hexagon::L2_loadri_io:
- case Hexagon::LDriw_f:
case Hexagon::S2_storeri_io:
- case Hexagon::STriw_f:
return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
(Offset <= Hexagon_MEMW_OFFSET_MAX);
case Hexagon::L2_loadrd_io:
case Hexagon::S2_storerd_io:
- case Hexagon::STrid_f:
return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
(Offset <= Hexagon_MEMD_OFFSET_MAX);
@@ -1550,12 +1539,6 @@ int HexagonInstrInfo::GetDotNewOp(const
case Hexagon::STrih_shl_V4:
return Hexagon::STrih_shl_nv_V4;
- case Hexagon::STriw_f:
- return Hexagon::S2_storerinew_io;
-
- case Hexagon::STriw_indexed_f:
- return Hexagon::S4_storerinew_rr;
-
case Hexagon::STriw_shl_V4:
return Hexagon::STriw_shl_nv_V4;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=226065&r1=226064&r2=226065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Wed Jan 14 18:15:30 2015
@@ -2774,6 +2774,26 @@ defm storerd: ST_PostInc <"memd", "STrid
let accessSize = HalfWordAccess, isNVStorable = 0, isCodeGenOnly = 0 in
defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
+// Patterns for generating stores, where the address takes different forms:
+// - frameindex,,
+// - base + offset,
+// - simple (base address without offset).
+// These would usually be used together (via Storex_pat defined below), but
+// in some cases one may want to apply different properties (such as
+// AddedComplexity) to the individual patterns.
+class Storex_fi_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
+ : Pat<(Store Value:$Rs, AddrFI:$fi), (MI AddrFI:$fi, 0, Value:$Rs)>;
+class Storex_add_pat<PatFrag Store, PatFrag Value, PatFrag ImmPred,
+ InstHexagon MI>
+ : Pat<(Store Value:$Rt, (add (i32 IntRegs:$Rs), ImmPred:$Off)),
+ (MI IntRegs:$Rs, imm:$Off, Value:$Rt)>;
+
+multiclass Storex_pat<PatFrag Store, PatFrag Value, PatLeaf ImmPred,
+ InstHexagon MI> {
+ def: Storex_fi_pat <Store, Value, MI>;
+ def: Storex_add_pat <Store, Value, ImmPred, MI>;
+}
+
def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
s4_3ImmPred:$offset),
(S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td?rev=226065&r1=226064&r2=226065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV5.td Wed Jan 14 18:15:30 2015
@@ -112,8 +112,12 @@ def S5_popcountp : ALU64_rr<(outs IntReg
let Inst{20-16} = Rss;
}
+defm: Loadx_pat<load, f32, s11_2ExtPred, L2_loadri_io>;
defm: Loadx_pat<load, f64, s11_3ExtPred, L2_loadrd_io>;
+defm: Storex_pat<store, F32, s11_2ExtPred, S2_storeri_io>;
+defm: Storex_pat<store, F64, s11_3ExtPred, S2_storerd_io>;
+
let isFP = 1, hasNewValue = 1, opNewValue = 0 in
class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp>
: MInst<(outs IntRegs:$Rd),
@@ -485,59 +489,6 @@ def F2_dfimm_p : T_fimm <"dfmake", Doubl
def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>;
}
-let AddedComplexity = 20 in
-def LDrid_indexed_f : LDInst<(outs DoubleRegs:$dst),
- (ins IntRegs:$src1, s11_3Imm:$offset),
- "$dst = memd($src1+#$offset)",
- [(set DoubleRegs:$dst, (f64 (load (add IntRegs:$src1,
- s11_3ImmPred:$offset))))]>,
- Requires<[HasV5T]>;
-
-def LDriw_f : LDInst<(outs IntRegs:$dst),
- (ins MEMri:$addr), "$dst = memw($addr)",
- [(set IntRegs:$dst, (f32 (load ADDRriS11_2:$addr)))]>,
- Requires<[HasV5T]>;
-
-
-let AddedComplexity = 20 in
-def LDriw_indexed_f : LDInst<(outs IntRegs:$dst),
- (ins IntRegs:$src1, s11_2Imm:$offset),
- "$dst = memw($src1+#$offset)",
- [(set IntRegs:$dst, (f32 (load (add IntRegs:$src1,
- s11_2ImmPred:$offset))))]>,
- Requires<[HasV5T]>;
-
-// Store.
-def STriw_f : STInst<(outs),
- (ins MEMri:$addr, IntRegs:$src1),
- "memw($addr) = $src1",
- [(store (f32 IntRegs:$src1), ADDRriS11_2:$addr)]>,
- Requires<[HasV5T]>;
-
-let AddedComplexity = 10 in
-def STriw_indexed_f : STInst<(outs),
- (ins IntRegs:$src1, s11_2Imm:$src2, IntRegs:$src3),
- "memw($src1+#$src2) = $src3",
- [(store (f32 IntRegs:$src3),
- (add IntRegs:$src1, s11_2ImmPred:$src2))]>,
- Requires<[HasV5T]>;
-
-def STrid_f : STInst<(outs),
- (ins MEMri:$addr, DoubleRegs:$src1),
- "memd($addr) = $src1",
- [(store (f64 DoubleRegs:$src1), ADDRriS11_2:$addr)]>,
- Requires<[HasV5T]>;
-
-// Indexed store double word.
-let AddedComplexity = 10 in
-def STrid_indexed_f : STInst<(outs),
- (ins IntRegs:$src1, s11_3Imm:$src2, DoubleRegs:$src3),
- "memd($src1+#$src2) = $src3",
- [(store (f64 DoubleRegs:$src3),
- (add IntRegs:$src1, s11_3ImmPred:$src2))]>,
- Requires<[HasV5T]>;
-
-
// Add
let isCommutable = 1 in
def fADD_rr : ALU64_rr<(outs IntRegs:$dst),
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=226065&r1=226064&r2=226065&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Wed Jan 14 18:15:30 2015
@@ -164,8 +164,7 @@ void HexagonRegisterInfo::eliminateFrame
(MI.getOpcode() == Hexagon::L2_loadrh_io) ||
(MI.getOpcode() == Hexagon::L2_loadruh_io) ||
(MI.getOpcode() == Hexagon::L2_loadrb_io) ||
- (MI.getOpcode() == Hexagon::L2_loadrub_io) ||
- (MI.getOpcode() == Hexagon::LDriw_f)) {
+ (MI.getOpcode() == Hexagon::L2_loadrub_io)) {
unsigned dstReg = (MI.getOpcode() == Hexagon::L2_loadrd_io) ?
getSubReg(MI.getOperand(0).getReg(), Hexagon::subreg_loreg) :
MI.getOperand(0).getReg();
@@ -188,9 +187,7 @@ void HexagonRegisterInfo::eliminateFrame
} else if ((MI.getOpcode() == Hexagon::S2_storeri_io) ||
(MI.getOpcode() == Hexagon::S2_storerd_io) ||
(MI.getOpcode() == Hexagon::S2_storerh_io) ||
- (MI.getOpcode() == Hexagon::S2_storerb_io) ||
- (MI.getOpcode() == Hexagon::STrid_f) ||
- (MI.getOpcode() == Hexagon::STriw_f)) {
+ (MI.getOpcode() == Hexagon::S2_storerb_io)) {
// For stores, we need a reserved register. Change
// memw(r30 + #10000) = r0 to:
//
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