[PATCH][mips] Refine octeon instructions seq/seqi/sne/snei

Kai Nacke kai.nacke at redstar.de
Wed Jan 14 02:21:16 PST 2015

Thanks. Committed as r225968 with the test case changes.


On 13.01.2015 15:30, Daniel Sanders wrote:
> I've been wondering about the way we have comparisons defined to produce an i32 on MIPS64. It works, but I'm pretty sure it's wrong and should be i64 since the instructions used to implement it write i64 zero/one to the register. Unfortunately, I haven't had chance to look into changing it yet.
> LGTM with a nit:
> * As with the other patch, could you fill out the registers for the MIPS64 portions of the case too?
>> -----Original Message-----
>> From: Kai Nacke [mailto:kai.nacke at redstar.de]
>> Sent: 08 January 2015 16:32
>> To: Daniel Sanders; llvm-commits
>> Subject: [PATCH][mips] Refine octeon instructions seq/seqi/sne/snei
>> Hello Daniel!
>> The attached patch refines the pattern for the octeon seq/seqi/sne/snei
>> instructions.
>> The target register is set to 0 or 1 according to the result of the
>> comparison. In C, this is something like
>> rd = (long)(rs == rt)
>> The attached patch adds a zext to bring the result to i64. With this
>> change the instruction is selected for this type of code. (This is the
>> same which gcc produces for the C code.)
>> Please review.
>> Regards,
>> Kai

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