[PATCH] [ARM] Fix large stack alignment codegen bug for ARM and Thumb2 targets

[Kristof Beyls]

Hi t.p.northover,

This patch partially fixes PR13007 (ARM CodeGen fails with large
stack alignment): for ARM and Thumb2 targets, but not for Thumb1,
as it seems stack alignment for Thumb1 targets hasn't been
supported at all.

Producing an aligned stack pointer is done by zero-ing out the lower
bits of the stack pointer. The BIC instruction was used for this.
However, the immediate field of the BIC instruction only allows to
encode an immediate that can zero out up to a maximum of the 8 lower
bits. When a larger alignment is requested, a BIC instruction cannot
be used; llvm was silently producing incorrect code in this case.

This patch fixes code generation for large stack aligments by using
the BFC instruction instead, when the BFC instruction is available.
When not, it uses 2 instructions: a right shift, followed by a left
shift to zero out the lower bits.

The lowering of ARM::Int_eh_sjlj_dispatchsetup still has code
that unconditionally uses BIC to realign the stack pointer, so it
very likely has the same problem. However, I haven't been able to
produce a test case for that. Does anyone understand sjlj exception
handling well enough to produce a test case triggering the bug on
the FIXME I've added in ARMExpandPseudoInsts.cpp?

Please review!

Thanks,

Kristof

REPOSITORY
  rL LLVM

http://reviews.llvm.org/D6844

Files:
  lib/Target/ARM/ARMExpandPseudoInsts.cpp
  lib/Target/ARM/ARMFrameLowering.cpp
  test/CodeGen/ARM/alloc-no-stack-realign.ll
  test/CodeGen/ARM/fold-stack-adjust.ll
  test/CodeGen/ARM/interrupt-attr.ll
  test/CodeGen/ARM/spill-q.ll
  test/CodeGen/ARM/stack-alignment.ll
  test/CodeGen/Thumb2/aligned-spill.ll
  test/CodeGen/Thumb2/thumb2-spill-q.ll

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