[PATCH] [AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.

[Ahmed Bougacha]

Hi jmolloy,

Split out of D6202.

For 0-lane stores, we used to generate stuff like:

```
	fmov w8, s0
	str w8, [x0, x1, lsl #2]
```
instead of:

```
	str s0, [x0, x1, lsl #2]

```
To correct that: for store lane 0 patterns, directly match to STR <subreg>0

Byte-sized instructions don't have the special case for a 0 index, because FPR8s are defined to have untyped content.

http://reviews.llvm.org/D6772

Files:
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-st1.ll

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