Subject: r223862 - caused regressions in internal tests

[Ahmed Bougacha]

Ah I think I see the issue here.  The alignment is off; the selection
logic for vld/vst doesn't care about less-than-standard alignment
attributes.  In this case, the alignment of the loads is 1, but
SelectVLD selected VLD1q64, because the result type was v2i64.  It was
obvious from the testcases I added in that commit, but for some reason
I didn't register the wrongness.

I have a patch to introduce bitcasts if necessary, and change the
vld/vst type to one whose standard alignment matches the original
load/store alignment.

I attached it; can you (or Ranjeet) verify it unbreaks this testcase?
With it, the assembly looks correct (uses vld1.8), and on my device
there was no problem before or after (alignment leniency does
wonders).
I'll try to enable alignment checking, but I'm not sure how easy that will be.

Anyway, I don't see anything else that might be wrong; pointers appreciated!

Sorry about the breakage,

- Ahmed


On Fri, Dec 19, 2014 at 10:23 AM, Richard Barton <richard.barton at arm.com> wrote:
> Hi Ahmed,
>
> I am going off on hols for two weeks, so please cc Ranjeet in your reply.
>
> This commit broke some of our internal runtime tests on cortex-a9 and
> 8-A.32, I've created a simple reproducer below:
>
> #include <stdlib.h>
>
> int main() {
>     char szNumbers[] = "250068492 7b06af00 1100011011110101010001100000
> 0x6fffff";
>     char * pEnd;
>     unsigned long long int ulli1;
>     ulli1 = strtoull (szNumbers, &pEnd, 10);
>     return 0;
> }
>
> $ clang -mcpu=cortex-a9 --target=armv7a-none-eabi -std=c99 -mthumb -O0
> -fno-builtin -pedantic -Iinclude -INone test.c -o test
>
> The diff between the assembly produced without this patch and with it is
> below
>
>     add.w   r12, r3, #32
>     vld1.8  {d16, d17}, [r12]
>     vst1.64 {d16, d17}, [r2]
> -   add.w   r2, r1, #16
> -   add.w   r12, r3, #16
> -   vld1.8  {d16, d17}, [r12]
> -   vst1.64 {d16, d17}, [r2]
> +   vld1.64 {d16, d17}, [r3]!
> +   mov r2, r1
> +   vst1.64 {d16, d17}, [r2:64]!
>     vld1.8  {d16, d17}, [r3]
> -   vst1.64 {d16, d17}, [r1]
> +   vst1.64 {d16, d17}, [r2]
>
> Could you please investigate?
>
> Thanks,
> Ranjeet
>
>
>
>
>
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