[PATCH] [ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes

[Hao Liu]

Hi Bradley,

AArch64 backend also has such instructions (It even support double type), but it doesn't have such combine function to do such optimization. I think maybe we can also port this function to AArch64 backend.

Thanks,
-Hao


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  rL LLVM

http://reviews.llvm.org/D6657

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