[llvm] r224079 - R600/SI: Handle physical registers in getOpRegClass

Matt Arsenault Matthew.Arsenault at amd.com
Thu Dec 11 15:37:35 PST 2014


Author: arsenm
Date: Thu Dec 11 17:37:34 2014
New Revision: 224079

URL: http://llvm.org/viewvc/llvm-project?rev=224079&view=rev
Log:
R600/SI: Handle physical registers in getOpRegClass

Modified:
    llvm/trunk/lib/Target/R600/SIInstrInfo.cpp

Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.cpp?rev=224079&r1=224078&r2=224079&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.cpp Thu Dec 11 17:37:34 2014
@@ -1242,8 +1242,13 @@ const TargetRegisterClass *SIInstrInfo::
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   const MCInstrDesc &Desc = get(MI.getOpcode());
   if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
-      Desc.OpInfo[OpNo].RegClass == -1)
-    return MRI.getRegClass(MI.getOperand(OpNo).getReg());
+      Desc.OpInfo[OpNo].RegClass == -1) {
+    unsigned Reg = MI.getOperand(OpNo).getReg();
+
+    if (TargetRegisterInfo::isVirtualRegister(Reg))
+      return MRI.getRegClass(Reg);
+    return RI.getRegClass(Reg);
+  }
 
   unsigned RCID = Desc.OpInfo[OpNo].RegClass;
   return RI.getRegClass(RCID);





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