[llvm] r223680 - [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns.

[Colin LeMahieu]

Author: colinl
Date: Mon Dec  8 12:33:49 2014
New Revision: 223680

URL: http://llvm.org/viewvc/llvm-project?rev=223680&view=rev
Log:
[Hexagon] Adding add/sub with saturation.  Removing unused def.  Cleaning up shift patterns.

Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
    llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
    llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=223680&r1=223679&r2=223680&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Mon Dec  8 12:33:49 2014
@@ -170,6 +170,18 @@ def A2_combine_lh : T_ALU32_combineh<".l
 def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>;
 }
 
+class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
+                      bits<3> MinOp, bit OpsRev, bit IsComm>
+  : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> {
+  let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
+}
+
+let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123, 
+    isCodeGenOnly = 0 in {
+  def A2_addsat   : T_ALU32_3op_sfx<"add",    ":sat", 0b110, 0b010, 0, 1>;
+  def A2_subsat   : T_ALU32_3op_sfx<"sub",    ":sat", 0b110, 0b110, 1, 0>;
+}
+
 multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
                          bit OpsRev> {
   def t    : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;
@@ -834,11 +846,10 @@ multiclass ZXTB_base <string mnemonic, b
 let isCodeGenOnly=0 in
 defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel;
 
-let hasSideEffects = 0 in
-def COMBINE_ii : ALU32_ii<(outs DoubleRegs:$dst),
-            (ins s8Imm:$src1, s8Imm:$src2),
-            "$dst = combine(#$src1, #$src2)",
-            []>;
+def: Pat<(shl I32:$src1, (i32 16)),   (A2_aslh I32:$src1)>;
+def: Pat<(sra I32:$src1, (i32 16)),   (A2_asrh I32:$src1)>;
+def: Pat<(sext_inreg I32:$src1, i8),  (A2_sxtb I32:$src1)>;
+def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
 
 // Mux.
 def VMUX_prr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1,
@@ -847,17 +858,6 @@ def VMUX_prr64 : ALU64_rr<(outs DoubleRe
             "$dst = vmux($src1, $src2, $src3)",
             []>;
 
-def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
-           (A2_aslh IntRegs:$src1)>;
-
-def : Pat <(sra (i32 IntRegs:$src1), (i32 16)),
-           (A2_asrh IntRegs:$src1)>;
-
-def : Pat <(sext_inreg (i32 IntRegs:$src1), i8),
-           (A2_sxtb IntRegs:$src1)>;
-
-def : Pat <(sext_inreg (i32 IntRegs:$src1), i16),
-           (A2_sxth IntRegs:$src1)>;
 
 //===----------------------------------------------------------------------===//
 // ALU32/PERM -

Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td?rev=223680&r1=223679&r2=223680&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.td Mon Dec  8 12:33:49 2014
@@ -97,6 +97,12 @@ let Namespace = "Hexagon" in {
   def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
   def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
 
+  // Fake register to represent USR.OVF bit. Artihmetic/saturating instruc-
+  // tions modify this bit, and multiple such instructions are allowed in the
+  // same packet. We need to ignore output dependencies on this bit, but not
+  // on the entire USR.
+  def USR_OVF : Rc<?, "usr.ovf">;
+
   // Control registers.
   def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>;
   def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>;

Modified: llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt?rev=223680&r1=223679&r2=223680&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32_alu.txt Mon Dec  8 12:33:49 2014
@@ -4,6 +4,8 @@
 # CHECK: r17 = add(r21, #31)
 0x11 0xdf 0x15 0xf3
 # CHECK: r17 = add(r21, r31)
+0x11 0xdf 0x55 0xf6
+# CHECK: r17 = add(r21, r31):sat
 0x11 0xdf 0x15 0xf1
 # CHECK: r17 = and(r21, r31)
 0xf1 0xc3 0x15 0x76
@@ -20,6 +22,8 @@
 # CHECK: r17 = sub(#21, r31)
 0x11 0xdf 0x35 0xf3
 # CHECK: r17 = sub(r31, r21)
+0x11 0xdf 0xd5 0xf6
+# CHECK: r17 = sub(r31, r21):sat
 0x11 0xc0 0xbf 0x70
 # CHECK: r17 = sxtb(r31)
 0x15 0xc0 0x31 0x72