[llvm] r223510 - Use 32-bit ebp for NaCl64 in a limited case: llvm.frameaddress.
Jan Wen Voung
jvoung at google.com
Fri Dec 5 12:55:54 PST 2014
Author: jvoung
Date: Fri Dec 5 14:55:53 2014
New Revision: 223510
URL: http://llvm.org/viewvc/llvm-project?rev=223510&view=rev
Log:
Use 32-bit ebp for NaCl64 in a limited case: llvm.frameaddress.
Summary:
Follow up to [x32] "Use ebp/esp as frame and stack pointer":
http://reviews.llvm.org/D4617
In that earlier patch, NaCl64 was made to always use rbp.
That's needed for most cases because rbp should hold a full
64-bit address within the NaCl sandbox so that load/stores
off of rbp don't require sandbox adjustment (zeroing the top
32-bits, then filling those by adding r15).
However, llvm.frameaddress returns a pointer and pointers
are 32-bit for NaCl64. In this case, use ebp instead, which
will make the register copy type check. A similar mechanism
may be needed for llvm.eh.return, but is not added in this change.
Test Plan: test/CodeGen/X86/frameaddr.ll
Reviewers: dschuff, nadav
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D6514
Modified:
llvm/trunk/lib/Target/X86/X86FastISel.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
llvm/trunk/test/CodeGen/X86/frameaddr.ll
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=223510&r1=223509&r2=223510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Dec 5 14:55:53 2014
@@ -2143,14 +2143,14 @@ bool X86FastISel::fastLowerIntrinsicCall
case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
}
- // This needs to be set before we call getFrameRegister, otherwise we get
- // the wrong frame register.
+ // This needs to be set before we call getPtrSizedFrameRegister, otherwise
+ // we get the wrong frame register.
MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
MFI->setFrameAddressIsTaken(true);
const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
TM.getSubtargetImpl()->getRegisterInfo());
- unsigned FrameReg = RegInfo->getFrameRegister(*(FuncInfo.MF));
+ unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*(FuncInfo.MF));
assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
(FrameReg == X86::EBP && VT == MVT::i32)) &&
"Invalid Frame Register!");
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=223510&r1=223509&r2=223510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Dec 5 14:55:53 2014
@@ -17636,7 +17636,8 @@ SDValue X86TargetLowering::LowerFRAMEADD
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
DAG.getSubtarget().getRegisterInfo());
- unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
+ unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
+ DAG.getMachineFunction());
assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
(FrameReg == X86::EBP && VT == MVT::i32)) &&
"Invalid Frame Register!");
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=223510&r1=223509&r2=223510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Dec 5 14:55:53 2014
@@ -535,6 +535,14 @@ unsigned X86RegisterInfo::getFrameRegist
return TFI->hasFP(MF) ? FramePtr : StackPtr;
}
+unsigned X86RegisterInfo::getPtrSizedFrameRegister(
+ const MachineFunction &MF) const {
+ unsigned FrameReg = getFrameRegister(MF);
+ if (Subtarget.isTarget64BitILP32())
+ FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
+ return FrameReg;
+}
+
namespace llvm {
unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
bool High) {
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=223510&r1=223509&r2=223510&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Fri Dec 5 14:55:53 2014
@@ -122,6 +122,7 @@ public:
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const override;
+ unsigned getPtrSizedFrameRegister(const MachineFunction &MF) const;
unsigned getStackRegister() const { return StackPtr; }
unsigned getBaseRegister() const { return BasePtr; }
// FIXME: Move to FrameInfok
Modified: llvm/trunk/test/CodeGen/X86/frameaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/frameaddr.ll?rev=223510&r1=223509&r2=223510&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/frameaddr.ll (original)
+++ llvm/trunk/test/CodeGen/X86/frameaddr.ll Fri Dec 5 14:55:53 2014
@@ -4,6 +4,8 @@
; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -mtriple=x86_64-gnux32 | FileCheck %s --check-prefix=CHECK-X32ABI
; RUN: llc < %s -mtriple=x86_64-gnux32 -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-X32ABI
+; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=CHECK-NACL64
+; RUN: llc < %s -mtriple=x86_64-nacl -fast-isel -fast-isel-abort | FileCheck %s --check-prefix=CHECK-NACL64
define i8* @test1() nounwind {
entry:
@@ -25,6 +27,10 @@ entry:
; CHECK-X32ABI-NEXT: movl %ebp, %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
+; CHECK-NACL64-LABEL: test1
+; CHECK-NACL64: pushq %rbp
+; CHECK-NACL64-NEXT: movq %rsp, %rbp
+; CHECK-NACL64-NEXT: movl %ebp, %eax
%0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0
}
@@ -52,6 +58,11 @@ entry:
; CHECK-X32ABI-NEXT: movl (%eax), %eax
; CHECK-X32ABI-NEXT: popq %rbp
; CHECK-X32ABI-NEXT: ret
+; CHECK-NACL64-LABEL: test2
+; CHECK-NACL64: pushq %rbp
+; CHECK-NACL64-NEXT: movq %rsp, %rbp
+; CHECK-NACL64-NEXT: movl (%ebp), %eax
+; CHECK-NACL64-NEXT: movl (%eax), %eax
%0 = tail call i8* @llvm.frameaddress(i32 2)
ret i8* %0
}
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