[PATCH] combine consecutive subvector 16-byte loads into one 32-byte load (PR21709)

[Sanjay Patel]

Hi Elena - thanks for your feedback! Updated patch attached.

I've added test cases that use shufflevector rather than the vinsertf128 intrinsic. This is derived from Andrea's alternate code example in the bug report. Does this cover the scenario you're thinking about using insertelement(s)? Unless I'm mistaken, we can only use insertelement with scalars, so this would be the expected pattern from IR that had insert/extract?

I've also added test cases that swap the order of the operands to the intrinsic and shuffles. Does this answer your concern about changing the order of the pattern parameters?

http://reviews.llvm.org/D6492

Files:
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/unaligned-32-byte-memops.ll
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