[PATCH] Target: Add ParserMatchClass field to RegisterClass

[Tom Stellard]

This allows targets to specify an AsmOperandClass for registers
without having to wrap the RegisterClass in a RegisterOperand.
---
 include/llvm/Target/Target.td        | 4 ++++
 utils/TableGen/AsmMatcherEmitter.cpp | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 902647e..7f26edc 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -20,6 +20,7 @@ include "llvm/IR/Intrinsics.td"
 // description classes.
 
 class RegisterClass; // Forward def
+class AsmOperandClass; // Forward def
 
 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
 class SubRegIndex<int size, int offset = 0> {
@@ -207,6 +208,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // The function should return 0 to select the default order defined by
   // MemberList, 1 to select the first AltOrders entry and so on.
   code AltOrderSelect = [{}];
+
+  // Operand class for this register
+  AsmOperandClass ParserMatchClass;
 }
 
 // The memberList in a RegisterClass is a dag of set operations. TableGen
diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp
index 891328f..143a358 100644
--- a/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1047,6 +1047,14 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
 
 
   if (Rec->isSubClassOf("RegisterClass")) {
+    const RecordVal *R = Rec->getValue("ParserMatchClass");
+    if (R && R->getValue()) {
+      if (DefInit *DI = dyn_cast<DefInit>(R->getValue())) {
+        Record *MatchClass = DI->getDef();
+        if (ClassInfo *CI = AsmOperandClasses[MatchClass])
+          return CI;
+      }
+    }
     if (ClassInfo *CI = RegisterClassClasses[Rec])
       return CI;
     PrintFatalError(Rec->getLoc(), "register class has no class info!");
-- 
1.8.1.5