[PATCH] combine consecutive subvector 16-byte loads into one 32-byte load (PR21709)

[Sanjay Patel]

Hi craig.topper, delena, andreadb,

This is a partial fix for PR21709 ( http://llvm.org/bugs/show_bug.cgi?id=21709 ). When we have 2 consecutive 16-byte loads that are merged into one 32-byte vector, we can use a single 32-byte load instead. But we don't do this for SandyBridge / IvyBridge because they have slower 32-byte memops.

I'm not too confident in my tablegen skills yet, so I've left the full list of pattern possibilities out of this patch until I get this one right. There's a 'TODO' comment where I think we'll want to add more patterns.

http://reviews.llvm.org/D6492

Files:
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86InstrSSE.td
  test/CodeGen/X86/unaligned-32-byte-memops.ll
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