[llvm] r223180 - AArch64: strengthen Darwin ABI alignment assumptions

[Tim Northover]

Author: tnorthover
Date: Tue Dec  2 17:53:43 2014
New Revision: 223180

URL: http://llvm.org/viewvc/llvm-project?rev=223180&view=rev
Log:
AArch64: strengthen Darwin ABI alignment assumptions

A global variable without an explicit alignment specified should be assumed to
be ABI-aligned according to its type, like on other platforms. This allows us
to use better memory operations when accessing it.

rdar://18533701

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/AArch64/arm64-promote-const.ll
    llvm/trunk/test/CodeGen/AArch64/global-merge-1.ll
    llvm/trunk/test/CodeGen/AArch64/global-merge-2.ll

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=223180&r1=223179&r2=223180&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Tue Dec  2 17:53:43 2014
@@ -615,7 +615,7 @@ bool AArch64DAGToDAGISel::SelectAddrMode
     unsigned Alignment = GV->getAlignment();
     const DataLayout *DL = TLI->getDataLayout();
     Type *Ty = GV->getType()->getElementType();
-    if (Alignment == 0 && Ty->isSized() && !Subtarget->isTargetDarwin())
+    if (Alignment == 0 && Ty->isSized())
       Alignment = DL->getABITypeAlignment(Ty);
 
     if (Alignment >= Size)

Modified: llvm/trunk/test/CodeGen/AArch64/arm64-promote-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-promote-const.ll?rev=223180&r1=223179&r2=223180&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-promote-const.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-promote-const.ll Tue Dec  2 17:53:43 2014
@@ -41,8 +41,7 @@ entry:
 ; PROMOTED-LABEL: test2:
 ; In stress mode, constant vector are promoted
 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
+; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
 ; Destination register is defined by ABI
 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
 ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]]
@@ -72,15 +71,13 @@ define <16 x i8> @test3(<16 x i8> %arg,
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
+; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
 ; Destination register is defined by ABI
 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
 ; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]]
 ; Next BB
 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV2]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[BASEADDR]]]
+; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTV2]]@PAGEOFF]
 ; Next BB
 ; PROMOTED-NEXT: [[LABEL]]:
 ; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]
@@ -136,8 +133,7 @@ define <16 x i8> @test4(<16 x i8> %arg,
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
+; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
 ; Destination register is defined by ABI
 ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]]
 ; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
@@ -185,8 +181,7 @@ define <16 x i8> @test5(<16 x i8> %arg,
 ; Since, the constant is the same as the previous function,
 ; the same address must be used
 ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE
-; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF
-; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]]
+; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF]
 ; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]]
 ; Next BB
 ; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]]

Modified: llvm/trunk/test/CodeGen/AArch64/global-merge-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/global-merge-1.ll?rev=223180&r1=223179&r2=223180&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/global-merge-1.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/global-merge-1.ll Tue Dec  2 17:53:43 2014
@@ -11,6 +11,7 @@
 @n = internal global i32 0, align 4
 
 define void @f1(i32 %a1, i32 %a2) {
+;CHECK-APPLE-IOS-NOT: adrp
 ;CHECK-APPLE-IOS: adrp	x8, __MergedGlobals at PAGE
 ;CHECK-APPLE-IOS-NOT: adrp
 ;CHECK-APPLE-IOS: add	x8, x8, __MergedGlobals at PAGEOFF

Modified: llvm/trunk/test/CodeGen/AArch64/global-merge-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/global-merge-2.ll?rev=223180&r1=223179&r2=223180&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/global-merge-2.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/global-merge-2.ll Tue Dec  2 17:53:43 2014
@@ -8,6 +8,7 @@
 
 define void @f1(i32 %a1, i32 %a2) {
 ;CHECK-APPLE-IOS-LABEL: _f1:
+;CHECK-APPLE-IOS-NOT: adrp
 ;CHECK-APPLE-IOS: adrp	x8, __MergedGlobals_x at PAGE
 ;CHECK-APPLE-IOS: add	x8, x8, __MergedGlobals_x at PAGEOFF
 ;CHECK-APPLE-IOS-NOT: adrp