[PATCH] AVX-512 ERI Instrinsics for scalar instructions

[Adam Nemet]

Sorry about the delay responding, I was on vacation.  I see you already committed this.  I think this looks good.  I just have a few comments that would be good to fix.

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Comment at: lib/Target/X86/X86ISelLowering.cpp:16802-16805
@@ -16801,1 +16801,6 @@
 
+static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
+                                    SDValue PreservedSrc,
+                                    const X86Subtarget *Subtarget,
+                                    SelectionDAG &DAG) {
+    EVT VT = Op.getValueType();
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Please add comment, especially the difference from getVectorMaskingNode that you explained in the patch comment.

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Comment at: lib/Target/X86/X86InstrAVX512.td:26-31
@@ -25,4 +25,8 @@
 
-  string VTName = "v" # NumElts # EltVT;
+  int NumEltsInVT = !if (!eq (NumElts, 1),
+                         !if (!eq (EltVT.Size, 32), 4,
+                         !if (!eq (EltVT.Size, 64), 2, NumElts)), NumElts);
+                         
+  string VTName = "v" # NumEltsInVT # EltVT;
 
   // The vector VT.
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I think that this needs a comment and a better name.  This is more like the number of elements in the *RC* not in the VT, right?

You should probably also add a comment before X86VTVectorInfo that for scalar types in vector registers they are essentially treated as occupying the entire 128-bit vector register with the appropriate number of upper elements ignored (probably with some examples).

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Comment at: lib/Target/X86/X86InstrAVX512.td:124-126
@@ -117,1 +123,5 @@
+// the scalar staff
+def f32x_info    : X86VectorVTInfo<1,  f32, VR128X, "ss">;
+def f64x_info    : X86VectorVTInfo<1,  f64, VR128X, "sd">;
+
 class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
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Why not FR32X and FR64X for RC?

http://reviews.llvm.org/D6378