[llvm] r222899 - [mips] Add synci instruction.
Daniel Sanders
daniel.sanders at imgtec.com
Thu Nov 27 09:28:10 PST 2014
Author: dsanders
Date: Thu Nov 27 11:28:10 2014
New Revision: 222899
URL: http://llvm.org/viewvc/llvm-project?rev=222899&view=rev
Log:
[mips] Add synci instruction.
Patch by Amaury Pouly
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6421
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
llvm/trunk/test/MC/Mips/mips32r2/valid.s
llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Thu Nov 27 11:28:10 2014
@@ -252,6 +252,11 @@ static DecodeStatus DecodeCacheOp(MCInst
uint64_t Address,
const void *Decoder);
+static DecodeStatus DecodeSyncI(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
@@ -1064,6 +1069,21 @@ static DecodeStatus DecodeCacheOp(MCInst
return MCDisassembler::Success;
}
+
+static DecodeStatus DecodeSyncI(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder) {
+ int Offset = SignExtend32<16>(Insn & 0xffff);
+ unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+ Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
+
+ Inst.addOperand(MCOperand::CreateReg(Base));
+ Inst.addOperand(MCOperand::CreateImm(Offset));
+
+ return MCDisassembler::Success;
+}
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Thu Nov 27 11:28:10 2014
@@ -411,6 +411,20 @@ class SYNC_FM : StdArch {
let Inst{5-0} = 0xf;
}
+class SYNCI_FM : StdArch {
+ // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
+ bits<21> addr;
+ bits<5> rs = addr{20-16};
+ bits<16> offset = addr{15-0};
+
+ bits<32> Inst;
+
+ let Inst{31-26} = 0b000001;
+ let Inst{25-21} = rs;
+ let Inst{20-16} = 0b11111;
+ let Inst{15-0} = offset;
+}
+
class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
bits<5> rs;
bits<5> rt;
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Thu Nov 27 11:28:10 2014
@@ -425,7 +425,14 @@ def MipsMemSimm11AsmOperand : AsmOperand
let RenderMethod = "addMemOperands";
let ParserMethod = "parseMemOperand";
let PredicateMethod = "isMemWithSimmOffset<11>";
- //let DiagnosticType = "Simm11";
+}
+
+def MipsMemSimm16AsmOperand : AsmOperandClass {
+ let Name = "MemOffsetSimm16";
+ let SuperClasses = [MipsMemAsmOperand];
+ let RenderMethod = "addMemOperands";
+ let ParserMethod = "parseMemOperand";
+ let PredicateMethod = "isMemWithSimmOffset<16>";
}
def MipsInvertedImmoperand : AsmOperandClass {
@@ -470,6 +477,12 @@ def mem_simm11 : mem_generic {
let ParserMatchClass = MipsMemSimm11AsmOperand;
}
+def mem_simm16 : mem_generic {
+ let MIOperandInfo = (ops ptr_rc, simm16);
+ let EncoderMethod = "getMemEncoding";
+ let ParserMatchClass = MipsMemSimm16AsmOperand;
+}
+
def mem_ea : Operand<iPTR> {
let PrintMethod = "printMemOperandEA";
let MIOperandInfo = (ops ptr_rc, simm16);
@@ -860,6 +873,13 @@ class SYNC_FT<string opstr> :
InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
NoItinerary, FrmOther, opstr>;
+class SYNCI_FT<string opstr> :
+ InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
+ NoItinerary, FrmOther, opstr> {
+ let hasSideEffects = 1;
+ let DecoderMethod = "DecodeSyncI";
+}
+
let hasSideEffects = 1 in
class TEQ_FT<string opstr, RegisterOperand RO> :
InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
@@ -1209,6 +1229,7 @@ let DecoderNamespace = "COP3_" in {
}
def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
+def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt Thu Nov 27 11:28:10 2014
@@ -448,3 +448,6 @@
# CHECK: xori $9, $6, 17767
0x38 0xc9 0x45 0x67
+
+# CHECK: synci -6137($fp)
+0x07 0xdf 0xe8 0x07
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt Thu Nov 27 11:28:10 2014
@@ -448,3 +448,6 @@
# CHECK: xori $9, $6, 17767
0x67 0x45 0xc9 0x38
+
+# CHECK: synci 7500($19)
+0x4c 0x1d 0x7f 0x06
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid-xfail.s Thu Nov 27 11:28:10 2014
@@ -293,7 +293,6 @@
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
- synci 20023($s0)
tlbginv
tlbginvf
tlbgp
Modified: llvm/trunk/test/MC/Mips/mips32r2/valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips32r2/valid.s?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s (original)
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s Thu Nov 27 11:28:10 2014
@@ -233,3 +233,4 @@
trunc.w.s $f28,$f30
wsbh $k1,$9
xor $s2,$a0,$s8
+ synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
Modified: llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s?rev=222899&r1=222898&r2=222899&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s (original)
+++ llvm/trunk/test/MC/Mips/mips64r2/valid-xfail.s Thu Nov 27 11:28:10 2014
@@ -297,7 +297,6 @@
swe $24,94($k0)
swle $v1,-209($gp)
swre $k0,-202($s2)
- synci 20023($s0)
tlbginv
tlbginvf
tlbgp
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