[llvm] r222844 - R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies

[Matt Arsenault]

Author: arsenm
Date: Wed Nov 26 12:18:28 2014
New Revision: 222844

URL: http://llvm.org/viewvc/llvm-project?rev=222844&view=rev
Log:
R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies

This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

Modified:
    llvm/trunk/lib/Target/R600/SILowerI1Copies.cpp

Modified: llvm/trunk/lib/Target/R600/SILowerI1Copies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerI1Copies.cpp?rev=222844&r1=222843&r2=222844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SILowerI1Copies.cpp (original)
+++ llvm/trunk/lib/Target/R600/SILowerI1Copies.cpp Wed Nov 26 12:18:28 2014
@@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFuncti
 
       if (MI.getOpcode() == AMDGPU::V_AND_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_OR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64));
         continue;
       }