[llvm] r222355 - [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.

[Jozef Kolek]

Author: jkolek
Date: Wed Nov 19 07:37:51 2014
New Revision: 222355

URL: http://llvm.org/viewvc/llvm-project?rev=222355&view=rev
Log:
[mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.

Differential Revision: http://reviews.llvm.org/D6169

Modified:
    llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
    llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s

Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=222355&r1=222354&r2=222355&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Wed Nov 19 07:37:51 2014
@@ -123,10 +123,10 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR
                              II_MFC1, bitconvert>, MFC1_FM_MM<0x80>;
 def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
                              II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>;
-def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
-               MFC1_FM_MM<3>, ISA_MIPS32R2;
-def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
-               MFC1_FM_MM<7>, ISA_MIPS32R2;
+def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
+               MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
+def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
+               MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>;
 
 def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
                 MADDS_FM_MM<0x1>;

Modified: llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s?rev=222355&r1=222354&r2=222355&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s Wed Nov 19 07:37:51 2014
@@ -53,6 +53,8 @@
 # CHECK-EL: ctc1    $6, $0              # encoding: [0xc0,0x54,0x3b,0x18]
 # CHECK-EL: mfc1    $6, $f8             # encoding: [0xc8,0x54,0x3b,0x20]
 # CHECK-EL: mtc1    $6, $f8             # encoding: [0xc8,0x54,0x3b,0x28]
+# CHECK-EL: mfhc1   $6, $f8             # encoding: [0xc8,0x54,0x3b,0x30]
+# CHECK-EL: mthc1   $6, $f8             # encoding: [0xc8,0x54,0x3b,0x38]
 # CHECK-EL: movz.s  $f4, $f6, $7        # encoding: [0xe6,0x54,0x78,0x20]
 # CHECK-EL: movz.d  $f4, $f6, $7        # encoding: [0xe6,0x54,0x78,0x21]
 # CHECK-EL: movn.s  $f4, $f6, $7        # encoding: [0xe6,0x54,0x38,0x20]
@@ -116,6 +118,8 @@
 # CHECK-EB: ctc1    $6, $0              # encoding: [0x54,0xc0,0x18,0x3b]
 # CHECK-EB: mfc1    $6, $f8             # encoding: [0x54,0xc8,0x20,0x3b]
 # CHECK-EB: mtc1    $6, $f8             # encoding: [0x54,0xc8,0x28,0x3b]
+# CHECK-EB: mfhc1   $6, $f8             # encoding: [0x54,0xc8,0x30,0x3b]
+# CHECK-EB: mthc1   $6, $f8             # encoding: [0x54,0xc8,0x38,0x3b]
 # CHECK-EB: movz.s  $f4, $f6, $7        # encoding: [0x54,0xe6,0x20,0x78]
 # CHECK-EB: movz.d  $f4, $f6, $7        # encoding: [0x54,0xe6,0x21,0x78]
 # CHECK-EB: movn.s  $f4, $f6, $7        # encoding: [0x54,0xe6,0x20,0x38]
@@ -175,6 +179,8 @@
     ctc1       $6, $0
     mfc1       $6, $f8
     mtc1       $6, $f8
+    mfhc1      $6, $f8
+    mthc1      $6, $f8
     movz.s     $f4, $f6, $7
     movz.d     $f4, $f6, $7
     movn.s     $f4, $f6, $7