[PATCH] R600/SI: Implement areMemAccessesTriviallyDisjoint

[Matt Arsenault]

> On Nov 6, 2014, at 12:26 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
> 
> 
>> On Oct 15, 2014, at 4:11 PM, Matt Arsenault <Matthew.Arsenault at amd.com> wrote:
>> 
>> On 09/17/2014 11:03 AM, Matt Arsenault wrote:
>>> On Sep 10, 2014, at 4:01 PM, Matt Arsenault <arsenm2 at gmail.com> wrote:
>>> 
>>>> Hi,
>>>> 
>>>> These implement the new areMemAccessesTriviallyDisjoint and enable AA during scheduling for when misched is enabled
>>>> 
>>> 
>>> 
>>> ping
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> ping
> 
> ping

Updated patches. Does not include enabling it now since enabling it breaks several tests with scheduling regressions


-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0001-R600-SI-Set-hasSideEffects-0-on-load-and-store-instr.patch
Type: application/octet-stream
Size: 3028 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141114/37fc5cfc/attachment.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 0002-R600-SI-Implement-areMemAccessesTriviallyDisjoint.patch
Type: application/octet-stream
Size: 15705 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20141114/37fc5cfc/attachment-0001.obj>