[llvm] r220704 - [FastISel][AArch64] Don't fold the 'and' instruction into the 'tbz/tbnz' instruction if it is in a different basic block.
Juergen Ributzka
juergen at apple.com
Mon Oct 27 12:16:48 PDT 2014
Author: ributzka
Date: Mon Oct 27 14:16:48 2014
New Revision: 220704
URL: http://llvm.org/viewvc/llvm-project?rev=220704&view=rev
Log:
[FastISel][AArch64] Don't fold the 'and' instruction into the 'tbz/tbnz' instruction if it is in a different basic block.
This fixes a bug where the input register was not defined for the 'tbz/tbnz'
instruction. This happened, because we folded the 'and' instruction from a
different basic block.
This fixes rdar://problem/18784013.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
llvm/trunk/test/CodeGen/AArch64/fast-isel-tbz.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=220704&r1=220703&r2=220704&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Mon Oct 27 14:16:48 2014
@@ -2118,7 +2118,7 @@ bool AArch64FastISel::emitCompareAndBran
return false;
if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
- if (AI->getOpcode() == Instruction::And) {
+ if (AI->getOpcode() == Instruction::And && isValueAvailable(AI)) {
const Value *AndLHS = AI->getOperand(0);
const Value *AndRHS = AI->getOperand(1);
@@ -2165,7 +2165,7 @@ bool AArch64FastISel::emitCompareAndBran
bool Is64Bit = BW == 64;
if (TestBit < 32 && TestBit >= 0)
Is64Bit = false;
-
+
unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
const MCInstrDesc &II = TII.get(Opc);
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-tbz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-tbz.ll?rev=220704&r1=220703&r2=220704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-tbz.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-tbz.ll Mon Oct 27 14:16:48 2014
@@ -121,5 +121,21 @@ bb2:
ret i32 0
}
+; Test that we don't fold the 'and' instruction into the compare.
+define i32 @icmp_eq_and_i32(i32 %a, i1 %c) {
+; CHECK-LABEL: icmp_eq_and_i32
+; CHECK: and [[REG:w[0-9]+]], w0, #0x4
+; CHECK-NEXT: cbz [[REG]], {{LBB.+_3}}
+ %1 = and i32 %a, 4
+ br i1 %c, label %bb0, label %bb2
+bb0:
+ %2 = icmp eq i32 %1, 0
+ br i1 %2, label %bb1, label %bb2, !prof !0
+bb1:
+ ret i32 1
+bb2:
+ ret i32 0
+}
+
!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647}
!1 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0}
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