[PATCH] [ARM] [CodeGen] Do not emit intermediate register for zero FP immediate

[Sergey Dmitrouk]

Hi Renato,

The thing with inline comments wasn't obvious for me :) I'm used to one email per comment.

Regards,
Sergey

================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:3246
@@ +3245,3 @@
+    // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
+    // created by LowerConstantFP().
+    SDValue BitcastOp = Op->getOperand(0);
----------------
rengolin wrote:
> sdmitrouk wrote:
> > rengolin wrote:
> > > I'd say this is a bit too specific on what LowerConstantFP does today, which may change. Wouldn't any fp bitcast work in this case, if the value being casted is zero?
> > Sure, it would work, but how to check node containing initial value for zero without going through all intermediate nodes? I was looking for a way to generalize this check, but didn't find it.
> I may be wrong, but wouldn't (Op->getValueType(0) == MVT::f32 || Op->getValueType(0) == MVT::f64) get all cases?
> 
> I don't expect vector types here, or half-floats...
I see it this way: if we need to check for immediate value the only way to do this is to walk through all intermediate nodes until we get to constant node containing the value.

Catching just zero immediate values or bitcasts to zero will ignore the one created by `LowerConstantFP`. It's a weird one, but the comment says "don't touch it for zero". `isFloatingPointZero` is called for arguments of comparison instructions to select special "compare with zero" form and zero argument is represented with such complex structure. I don't see a way to check for this "special zero" without hard-coding whole path to constant node somewhere.

http://reviews.llvm.org/D5456