[PATCH] [mips] Add support for COP0's Branch-On-Cond-Likely instructions

[Vasileios Kalintiris]

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Comment at: lib/Target/Mips/MipsInstrInfo.td:1230-1231
@@ -1217,2 +1229,4 @@
              ISA_MIPS1_NOT_32R6_64R6;
+def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd>,
+              BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
----------------
I will change the hasDelaySlot field for this likely instruction too since BGEZAL_FT sets it to 1.

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Comment at: lib/Target/Mips/MipsInstrInfo.td:1234-1235
@@ -1219,2 +1233,4 @@
              ISA_MIPS1_NOT_32R6_64R6;
+def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd>,
+              BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
----------------
I will change the hasDelaySlot field for this likely instruction too since BGEZAL_FT sets it to 1.

http://reviews.llvm.org/D5782