[llvm] r219999 - R600/SI: Simplify debug printing

Matt Arsenault Matthew.Arsenault at amd.com
Thu Oct 16 17:36:21 PDT 2014


Author: arsenm
Date: Thu Oct 16 19:36:20 2014
New Revision: 219999

URL: http://llvm.org/viewvc/llvm-project?rev=219999&view=rev
Log:
R600/SI: Simplify debug printing

Modified:
    llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp

Modified: llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp?rev=219999&r1=219998&r2=219999&view=diff
==============================================================================
--- llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp (original)
+++ llvm/trunk/lib/Target/R600/SIFixSGPRCopies.cpp Thu Oct 16 19:36:20 2014
@@ -243,7 +243,7 @@ bool SIFixSGPRCopies::runOnMachineFuncti
         // we must move it to the VALU, because the SGPR operands will
         // all end up being assigned the same register, which means
         // there is a potential for a conflict if different threads take
-	// different control flow paths.
+        // different control flow paths.
         //
         // For Example:
         //
@@ -305,8 +305,7 @@ bool SIFixSGPRCopies::runOnMachineFuncti
             !hasVGPROperands(MI, TRI))
           continue;
 
-        DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
-        DEBUG(MI.print(dbgs()));
+        DEBUG(dbgs() << "Fixing REG_SEQUENCE: " << MI);
 
         TII->moveToVALU(MI);
         break;
@@ -318,8 +317,7 @@ bool SIFixSGPRCopies::runOnMachineFuncti
         Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
         if (TRI->isSGPRClass(DstRC) &&
             (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
-          DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
-          DEBUG(MI.print(dbgs()));
+          DEBUG(dbgs() << " Fixing INSERT_SUBREG: " << MI);
           TII->moveToVALU(MI);
         }
         break;





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