[llvm] r219733 - ARM: allow misaligned local variables in Thumb1 mode.

[Tim Northover]

Author: tnorthover
Date: Tue Oct 14 17:12:14 2014
New Revision: 219733

URL: http://llvm.org/viewvc/llvm-project?rev=219733&view=rev
Log:
ARM: allow misaligned local variables in Thumb1 mode.

There's no hard requirement on LLVM to align local variable to 32-bits, so the
Thumb1 frame handling needs to be able to deal with variables that are only
naturally aligned without falling over.

Modified:
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/test/CodeGen/ARM/atomic-op.ll

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=219733&r1=219732&r2=219733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Tue Oct 14 17:12:14 2014
@@ -364,8 +364,6 @@ rewriteFrameIndex(MachineBasicBlock::ite
     } else {
       NumBits = 8;
       Scale = 4;
-      assert((Offset & 3) == 0 &&
-             "Thumb add/sub sp, #imm immediate must be multiple of 4!");
     }
 
     unsigned PredReg;
@@ -380,7 +378,7 @@ rewriteFrameIndex(MachineBasicBlock::ite
 
     // Common case: small offset, fits into instruction.
     unsigned Mask = (1 << NumBits) - 1;
-    if (((Offset / Scale) & ~Mask) == 0) {
+    if (Offset % Scale == 0 && ((Offset / Scale) & ~Mask) == 0) {
       // Replace the FrameIndex with sp / fp
       if (Opcode == ARM::tADDi3) {
         MI.setDesc(TII.get(Opcode));

Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=219733&r1=219732&r2=219733&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Tue Oct 14 17:12:14 2014
@@ -4,6 +4,8 @@
 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0
 ; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL
 
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+
 define void @func(i32 %argc, i8** %argv) nounwind {
 entry:
 	%argc.addr = alloca i32		; <i32*> [#uses=1]