[llvm] r219719 - ARM: set preferred aggregate alignment to 32 universally.

[Tim Northover]

Author: tnorthover
Date: Tue Oct 14 15:57:26 2014
New Revision: 219719

URL: http://llvm.org/viewvc/llvm-project?rev=219719&view=rev
Log:
ARM: set preferred aggregate alignment to 32 universally.

Before, ARM and Thumb mode code had different preferred alignments, which could
lead to some rather unexpected results. There's justification for reducing it
from the default 64-bits (wasted space), but I don't think there is for going
below 32-bits.

There's no actual ABI change here, just to reassure people.

Added:
    llvm/trunk/test/CodeGen/ARM/aggregate-align.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=219719&r1=219718&r2=219719&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Oct 14 15:57:26 2014
@@ -123,10 +123,9 @@ static std::string computeDataLayout(ARM
   else
     Ret += "-v128:64:128";
 
-  // On thumb and APCS, only try to align aggregates to 32 bits (the default is
-  // 64 bits).
-  if (ST.isThumb() || ST.isAPCS_ABI())
-    Ret += "-a:0:32";
+  // Try to align aggregates to 32 bits (the default is 64 bits, which has no
+  // particular hardware support on 32-bit ARM).
+  Ret += "-a:0:32";
 
   // Integer registers are 32 bits.
   Ret += "-n32";

Added: llvm/trunk/test/CodeGen/ARM/aggregate-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/aggregate-align.ll?rev=219719&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/aggregate-align.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/aggregate-align.ll Tue Oct 14 15:57:26 2014
@@ -0,0 +1,6 @@
+; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s
+
+ at var = global {i8, i8} zeroinitializer
+
+; CHECK: .globl var
+; CHECK-NEXT: .align 2