[llvm] r219705 - R600: Add new intrinsic to read work dimensions
Rafael Espíndola
rafael.espindola at gmail.com
Tue Oct 14 12:09:14 PDT 2014
I reverted since it was failing on linux:
/home/espindola/llvm/build/./bin/llc -march=r600 -mcpu=redwood <
/home/espindola/llvm/llvm/test/CodeGen/R600/work-item-intrinsics.ll |
/home/espindola/llvm/build/./bin/FileCheck -check-prefix=EG
-check-prefix=FUNC
/home/espindola/llvm/llvm/test/CodeGen/R600/work-item-intrinsics.ll
/home/espindola/llvm/build/./bin/llc -march=r600 -mcpu=SI
-verify-machineinstrs <
/home/espindola/llvm/llvm/test/CodeGen/R600/work-item-intrinsics.ll |
/home/espindola/llvm/build/./bin/FileCheck -check-prefix=SI
-check-prefix=FUNC
/home/espindola/llvm/llvm/test/CodeGen/R600/work-item-intrinsics.ll
--
Exit Code: 1
Command Output (stderr):
--
error: unsupported call to function llvm.r600.read.workdim in get_work_dim
/home/espindola/llvm/llvm/test/CodeGen/R600/work-item-intrinsics.ll:131:15:
error: expected string not found in input
; FUNC-LABEL: @get_work_dim
^
<stdin>:196:15: note: scanning from here
local_size_z: ; @local_size_z
^
<stdin>:196:19: note: possible intended match here
local_size_z: ; @local_size_z
On 14 October 2014 14:52, Jan Vesely <jan.vesely at rutgers.edu> wrote:
> Author: jvesely
> Date: Tue Oct 14 13:52:07 2014
> New Revision: 219705
>
> URL: http://llvm.org/viewvc/llvm-project?rev=219705&view=rev
> Log:
> R600: Add new intrinsic to read work dimensions
>
> v2: Add SI lowering
> Add test
>
> v3: Place work dimensions after the kernel arguments.
> v4: Calculate offset while lowering arguments
> v5: rebase
> v6: change prefix to AMDGPU
>
> Reviewed-by: Tom Stellard <tom at stellard.net>
> Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
>
> Modified:
> llvm/trunk/include/llvm/IR/IntrinsicsR600.td
> llvm/trunk/lib/Target/R600/AMDGPUMachineFunction.h
> llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> llvm/trunk/lib/Target/R600/SIISelLowering.cpp
> llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll
>
> Modified: llvm/trunk/include/llvm/IR/IntrinsicsR600.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsR600.td?rev=219705&r1=219704&r2=219705&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/IntrinsicsR600.td (original)
> +++ llvm/trunk/include/llvm/IR/IntrinsicsR600.td Tue Oct 14 13:52:07 2014
> @@ -33,10 +33,14 @@ defm int_r600_read_tgid : R600ReadPreloa
> "__builtin_r600_read_tgid">;
> defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <
> "__builtin_r600_read_tidig">;
> -
> } // End TargetPrefix = "r600"
>
> let TargetPrefix = "AMDGPU" in {
> +
> +class AMDGPUReadPreloadRegisterIntrinsic<string name>
> + : Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
> + GCCBuiltin<name>;
> +
> def int_AMDGPU_div_scale : GCCBuiltin<"__builtin_amdgpu_div_scale">,
> // 1st parameter: Numerator
> // 2nd parameter: Denominator
> @@ -72,4 +76,7 @@ def int_AMDGPU_rsq_clamped : GCCBuiltin<
> def int_AMDGPU_ldexp : GCCBuiltin<"__builtin_amdgpu_ldexp">,
> Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
>
> +def int_AMDGPU_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
> + "__builtin_amdgpu_read_workdim">;
> +
> } // End TargetPrefix = "AMDGPU"
>
> Modified: llvm/trunk/lib/Target/R600/AMDGPUMachineFunction.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUMachineFunction.h?rev=219705&r1=219704&r2=219705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/AMDGPUMachineFunction.h (original)
> +++ llvm/trunk/lib/Target/R600/AMDGPUMachineFunction.h Tue Oct 14 13:52:07 2014
> @@ -30,6 +30,9 @@ public:
> /// Number of bytes in the LDS that are being used.
> unsigned LDSSize;
>
> + /// Start of implicit kernel args
> + unsigned ABIArgOffset;
> +
> unsigned getShaderType() const {
> return ShaderType;
> }
>
> Modified: llvm/trunk/lib/Target/R600/R600ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600ISelLowering.cpp?rev=219705&r1=219704&r2=219705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/R600ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/R600ISelLowering.cpp Tue Oct 14 13:52:07 2014
> @@ -809,6 +809,9 @@ SDValue R600TargetLowering::LowerOperati
> case Intrinsic::r600_read_local_size_z:
> return LowerImplicitParameter(DAG, VT, DL, 8);
>
> + case Intrinsic::AMDGPU_read_workdim:
> + return LowerImplicitParameter(DAG, VT, DL, MFI->ABIArgOffset / 4);
> +
> case Intrinsic::r600_read_tgid_x:
> return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass,
> AMDGPU::T1_X, VT);
> @@ -1698,7 +1701,7 @@ SDValue R600TargetLowering::LowerFormalA
> CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
> *DAG.getContext());
> MachineFunction &MF = DAG.getMachineFunction();
> - unsigned ShaderType = MF.getInfo<R600MachineFunctionInfo>()->getShaderType();
> + R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
>
> SmallVector<ISD::InputArg, 8> LocalIns;
>
> @@ -1716,7 +1719,7 @@ SDValue R600TargetLowering::LowerFormalA
> MemVT = MemVT.getVectorElementType();
> }
>
> - if (ShaderType != ShaderType::COMPUTE) {
> + if (MFI->getShaderType() != ShaderType::COMPUTE) {
> unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass);
> SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT);
> InVals.push_back(Register);
> @@ -1748,16 +1751,18 @@ SDValue R600TargetLowering::LowerFormalA
>
> unsigned ValBase = ArgLocs[In.OrigArgIndex].getLocMemOffset();
> unsigned PartOffset = VA.getLocMemOffset();
> + unsigned Offset = 36 + VA.getLocMemOffset();
>
> MachinePointerInfo PtrInfo(UndefValue::get(PtrTy), PartOffset - ValBase);
> SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain,
> - DAG.getConstant(36 + PartOffset, MVT::i32),
> + DAG.getConstant(Offset, MVT::i32),
> DAG.getUNDEF(MVT::i32),
> PtrInfo,
> MemVT, false, true, true, 4);
>
> // 4 is the preferred alignment for the CONSTANT memory space.
> InVals.push_back(Arg);
> + MFI->ABIArgOffset = Offset + MemVT.getStoreSize();
> }
> return Chain;
> }
>
> Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=219705&r1=219704&r2=219705&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Tue Oct 14 13:52:07 2014
> @@ -519,11 +519,11 @@ SDValue SITargetLowering::LowerFormalArg
> if (VA.isMemLoc()) {
> VT = Ins[i].VT;
> EVT MemVT = Splits[i].VT;
> + const unsigned Offset = 36 + VA.getLocMemOffset();
> // The first 36 bytes of the input buffer contains information about
> // thread group and global sizes.
> SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, DAG.getRoot(),
> - 36 + VA.getLocMemOffset(),
> - Ins[i].Flags.isSExt());
> + Offset, Ins[i].Flags.isSExt());
>
> const PointerType *ParamTy =
> dyn_cast<PointerType>(FType->getParamType(Ins[i].OrigArgIndex));
> @@ -537,6 +537,7 @@ SDValue SITargetLowering::LowerFormalArg
> }
>
> InVals.push_back(Arg);
> + Info->ABIArgOffset = Offset + MemVT.getStoreSize();
> continue;
> }
> assert(VA.isRegLoc() && "Parameter must be in a register!");
> @@ -927,6 +928,12 @@ SDValue SITargetLowering::LowerINTRINSIC
> case Intrinsic::r600_read_local_size_z:
> return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
> +
> + case Intrinsic::AMDGPU_read_workdim:
> + return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
> + MF.getInfo<SIMachineFunctionInfo>()->ABIArgOffset,
> + false);
> +
> case Intrinsic::r600_read_tgid_x:
> return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
> TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
>
> Modified: llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll?rev=219705&r1=219704&r2=219705&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll (original)
> +++ llvm/trunk/test/CodeGen/R600/work-item-intrinsics.ll Tue Oct 14 13:52:07 2014
> @@ -128,6 +128,20 @@ entry:
> ret void
> }
>
> +; FUNC-LABEL: @get_work_dim
> +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
> +; EG: MOV [[VAL]], KC0[2].Z
> +
> +; SI: S_LOAD_DWORD [[VAL:s[0-9]+]], s[0:1], 0xb
> +; SI: V_MOV_B32_e32 [[VVAL:v[0-9]+]], [[VAL]]
> +; SI: BUFFER_STORE_DWORD [[VVAL]]
> +define void @get_work_dim (i32 addrspace(1)* %out) {
> +entry:
> + %0 = call i32 @llvm.r600.read.workdim() #0
> + store i32 %0, i32 addrspace(1)* %out
> + ret void
> +}
> +
> ; The tgid values are stored in sgprs offset by the number of user sgprs.
> ; Currently we always use exactly 2 user sgprs for the pointer to the
> ; kernel arguments, but this may change in the future.
> @@ -209,4 +223,6 @@ declare i32 @llvm.r600.read.tidig.x() #0
> declare i32 @llvm.r600.read.tidig.y() #0
> declare i32 @llvm.r600.read.tidig.z() #0
>
> +declare i32 @llvm.r600.read.workdim() #0
> +
> attributes #0 = { readnone }
>
>
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