[llvm] r219633 - Make first of several changes to bring up to AArch64 fast-isel style
Reed Kotler
rkotler at mips.com
Mon Oct 13 14:46:42 PDT 2014
Author: rkotler
Date: Mon Oct 13 16:46:41 2014
New Revision: 219633
URL: http://llvm.org/viewvc/llvm-project?rev=219633&view=rev
Log:
Make first of several changes to bring up to AArch64 fast-isel style
Summary:
Make Mips fast-isel track the form of AArch64 where practical.
This makes it easier for people to review the code, to borrow similar code, and to see how to eventually move a lot of this
target code for fast-isels into target independent code.
These are just cosmetic changes. Should be no functional difference.
Test Plan:
make check
test-suite for 4 flavors mips32 r1/r2 , -O0/-O2
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: aemerson, llvm-commits, rfuhler
Differential Revision: http://reviews.llvm.org/D5595
Modified:
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=219633&r1=219632&r2=219633&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Mon Oct 13 16:46:41 2014
@@ -18,23 +18,44 @@ using namespace llvm;
namespace {
-// All possible address modes.
-typedef struct Address {
- enum { RegBase, FrameIndexBase } BaseType;
-
- union {
- unsigned Reg;
- int FI;
- } Base;
-
- int64_t Offset;
-
- // Innocuous defaults for our address.
- Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; }
-} Address;
-
class MipsFastISel final : public FastISel {
+ // All possible address modes.
+ class Address {
+ public:
+ typedef enum { RegBase, FrameIndexBase } BaseKind;
+
+ private:
+ BaseKind Kind;
+ union {
+ unsigned Reg;
+ int FI;
+ } Base;
+
+ int64_t Offset;
+
+ const GlobalValue *GV;
+
+ public:
+ // Innocuous defaults for our address.
+ Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
+ void setKind(BaseKind K) { Kind = K; }
+ BaseKind getKind() const { return Kind; }
+ bool isRegBase() const { return Kind == RegBase; }
+ void setReg(unsigned Reg) {
+ assert(isRegBase() && "Invalid base register access!");
+ Base.Reg = Reg;
+ }
+ unsigned getReg() const {
+ assert(isRegBase() && "Invalid base register access!");
+ return Base.Reg;
+ }
+ void setOffset(int64_t Offset_) { Offset = Offset_; }
+ int64_t getOffset() const { return Offset; }
+ void setGlobalValue(const GlobalValue *G) { GV = G; }
+ const GlobalValue *getGlobalValue() { return GV; }
+ };
+
/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
/// make the right decision when generating code for different targets.
Module &M;
@@ -48,67 +69,68 @@ class MipsFastISel final : public FastIS
LLVMContext *Context;
bool TargetSupported;
- bool UnsupportedFPMode;
-
-public:
- explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
- const TargetLibraryInfo *libInfo)
- : FastISel(funcInfo, libInfo),
- M(const_cast<Module &>(*funcInfo.Fn->getParent())),
- TM(funcInfo.MF->getTarget()),
- TII(*TM.getSubtargetImpl()->getInstrInfo()),
- TLI(*TM.getSubtargetImpl()->getTargetLowering()),
- Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
- MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
- Context = &funcInfo.Fn->getContext();
- TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
- ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
- (Subtarget->isABI_O32())));
- UnsupportedFPMode = Subtarget->isFP64bit();
- }
-
- bool fastSelectInstruction(const Instruction *I) override;
- unsigned fastMaterializeConstant(const Constant *C) override;
-
- bool ComputeAddress(const Value *Obj, Address &Addr);
+ bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
+ // floating point but not reject doing fast-isel in other
+ // situations
private:
- bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
- unsigned Alignment = 0);
- bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
- unsigned Alignment = 0);
- bool EmitCmp(unsigned DestReg, const CmpInst *CI);
- bool SelectLoad(const Instruction *I);
- bool SelectBranch(const Instruction *I);
- bool SelectRet(const Instruction *I);
- bool SelectStore(const Instruction *I);
- bool SelectIntExt(const Instruction *I);
- bool SelectTrunc(const Instruction *I);
- bool SelectFPExt(const Instruction *I);
- bool SelectFPTrunc(const Instruction *I);
- bool SelectFPToI(const Instruction *I, bool IsSigned);
- bool SelectCmp(const Instruction *I);
+ // Selection routines.
+ bool selectLoad(const Instruction *I);
+ bool selectStore(const Instruction *I);
+ bool selectBranch(const Instruction *I);
+ bool selectCmp(const Instruction *I);
+ bool selectFPExt(const Instruction *I);
+ bool selectFPTrunc(const Instruction *I);
+ bool selectFPToInt(const Instruction *I, bool IsSigned);
+ bool selectRet(const Instruction *I);
+ bool selectTrunc(const Instruction *I);
+ bool selectIntExt(const Instruction *I);
+
+ // Utility helper routines.
bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT);
+ bool computeAddress(const Value *Obj, Address &Addr);
- unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
-
- unsigned MaterializeFP(const ConstantFP *CFP, MVT VT);
- unsigned MaterializeGV(const GlobalValue *GV, MVT VT);
- unsigned MaterializeInt(const Constant *C, MVT VT);
- unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
+ // Emit helper routines.
+ bool emitCmp(unsigned DestReg, const CmpInst *CI);
+ bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
+ unsigned Alignment = 0);
+ bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
+ unsigned Alignment = 0);
+ bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
- bool EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
bool IsZExt);
+ bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
- bool EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
-
- bool EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
- bool EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+ bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
+ bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg);
- bool EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+ bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg);
+
+ unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
+
+ unsigned materializeFP(const ConstantFP *CFP, MVT VT);
+ unsigned materializeGV(const GlobalValue *GV, MVT VT);
+ unsigned materializeInt(const Constant *C, MVT VT);
+ unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
+
+ MachineInstrBuilder emitInst(unsigned Opc) {
+ return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
+ }
+ MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
+ return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
+ DstReg);
+ }
+ MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
+ unsigned MemReg, int64_t MemOffset) {
+ return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
+ }
+ MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
+ unsigned MemReg, int64_t MemOffset) {
+ return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
+ }
// for some reason, this default is not generated by tablegen
// so we explicitly generate it here.
//
@@ -118,27 +140,31 @@ private:
return 0;
}
- MachineInstrBuilder EmitInst(unsigned Opc) {
- return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
- }
-
- MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) {
- return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
- DstReg);
- }
+public:
+ // Backend specific FastISel code.
- MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg,
- unsigned MemReg, int64_t MemOffset) {
- return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
+ explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
+ const TargetLibraryInfo *libInfo)
+ : FastISel(funcInfo, libInfo),
+ M(const_cast<Module &>(*funcInfo.Fn->getParent())),
+ TM(funcInfo.MF->getTarget()),
+ TII(*TM.getSubtargetImpl()->getInstrInfo()),
+ TLI(*TM.getSubtargetImpl()->getTargetLowering()),
+ Subtarget(&TM.getSubtarget<MipsSubtarget>()) {
+ MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
+ Context = &funcInfo.Fn->getContext();
+ TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) &&
+ ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
+ (Subtarget->isABI_O32())));
+ UnsupportedFPMode = Subtarget->isFP64bit();
}
- MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg,
- unsigned MemReg, int64_t MemOffset) {
- return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
- }
+ unsigned fastMaterializeConstant(const Constant *C) override;
+ bool fastSelectInstruction(const Instruction *I) override;
#include "MipsGenFastISel.inc"
};
+} // end anonymous namespace.
bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
EVT evt = TLI.getValueType(Ty, true);
@@ -163,7 +189,7 @@ bool MipsFastISel::isLoadTypeLegal(Type
return false;
}
-bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) {
+bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
// This construct looks a big awkward but it is how other ports handle this
// and as this function is more fully completed, these cases which
// return false will have additional code in them.
@@ -172,8 +198,8 @@ bool MipsFastISel::ComputeAddress(const
return false;
else if (isa<ConstantExpr>(Obj))
return false;
- Addr.Base.Reg = getRegForValue(Obj);
- return Addr.Base.Reg != 0;
+ Addr.setReg(getRegForValue(Obj));
+ return Addr.getReg() != 0;
}
unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
@@ -184,14 +210,14 @@ unsigned MipsFastISel::getRegEnsuringSim
MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- if (!EmitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
+ if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
return 0;
VReg = TempReg;
}
return VReg;
}
-bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
+bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
unsigned Alignment) {
//
// more cases will be handled here in following patches.
@@ -230,7 +256,7 @@ bool MipsFastISel::EmitLoad(MVT VT, unsi
default:
return false;
}
- EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset);
+ emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
return true;
}
@@ -245,16 +271,16 @@ unsigned MipsFastISel::fastMaterializeCo
MVT VT = CEVT.getSimpleVT();
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
- return (UnsupportedFPMode) ? 0 : MaterializeFP(CFP, VT);
+ return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
- return MaterializeGV(GV, VT);
+ return materializeGV(GV, VT);
else if (isa<ConstantInt>(C))
- return MaterializeInt(C, VT);
+ return materializeInt(C, VT);
return 0;
}
-bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr,
+bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
unsigned Alignment) {
//
// more cases will be handled here in following patches.
@@ -283,11 +309,11 @@ bool MipsFastISel::EmitStore(MVT VT, uns
default:
return false;
}
- EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset);
+ emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
return true;
}
-bool MipsFastISel::EmitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
unsigned ShiftAmt;
switch (SrcVT.SimpleTy) {
@@ -301,55 +327,55 @@ bool MipsFastISel::EmitIntSExt32r1(MVT S
break;
}
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
- EmitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
+ emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
+ emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
return true;
}
-bool MipsFastISel::EmitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
switch (SrcVT.SimpleTy) {
default:
return false;
case MVT::i8:
- EmitInst(Mips::SEB, DestReg).addReg(SrcReg);
+ emitInst(Mips::SEB, DestReg).addReg(SrcReg);
break;
case MVT::i16:
- EmitInst(Mips::SEH, DestReg).addReg(SrcReg);
+ emitInst(Mips::SEH, DestReg).addReg(SrcReg);
break;
}
return true;
}
-bool MipsFastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg, bool IsZExt) {
if (IsZExt)
- return EmitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
- return EmitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
+ return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
+ return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
}
-bool MipsFastISel::EmitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
return false;
if (Subtarget->hasMips32r2())
- return EmitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
- return EmitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
+ return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
+ return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
}
-bool MipsFastISel::EmitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
+bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
unsigned DestReg) {
switch (SrcVT.SimpleTy) {
default:
return false;
case MVT::i1:
- EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
+ emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
break;
case MVT::i8:
- EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
+ emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
break;
case MVT::i16:
- EmitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
+ emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
break;
}
return true;
@@ -359,7 +385,7 @@ bool MipsFastISel::EmitIntZExt(MVT SrcVT
// This can cause a redundant sltiu to be generated.
// FIXME: try and eliminate this in a future patch.
//
-bool MipsFastISel::SelectBranch(const Instruction *I) {
+bool MipsFastISel::selectBranch(const Instruction *I) {
const BranchInst *BI = cast<BranchInst>(I);
MachineBasicBlock *BrBB = FuncInfo.MBB;
//
@@ -375,7 +401,7 @@ bool MipsFastISel::SelectBranch(const In
// For now, just try the simplest case where it's fed by a compare.
if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
- if (!EmitCmp(CondReg, CI))
+ if (!emitCmp(CondReg, CI))
return false;
BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
.addReg(CondReg)
@@ -387,7 +413,7 @@ bool MipsFastISel::SelectBranch(const In
return false;
}
-bool MipsFastISel::SelectLoad(const Instruction *I) {
+bool MipsFastISel::selectLoad(const Instruction *I) {
// Atomic loads need special handling.
if (cast<LoadInst>(I)->isAtomic())
return false;
@@ -399,17 +425,17 @@ bool MipsFastISel::SelectLoad(const Inst
// See if we can handle this address.
Address Addr;
- if (!ComputeAddress(I->getOperand(0), Addr))
+ if (!computeAddress(I->getOperand(0), Addr))
return false;
unsigned ResultReg;
- if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
+ if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
return false;
updateValueMap(I, ResultReg);
return true;
}
-bool MipsFastISel::SelectStore(const Instruction *I) {
+bool MipsFastISel::selectStore(const Instruction *I) {
Value *Op0 = I->getOperand(0);
unsigned SrcReg = 0;
@@ -429,15 +455,15 @@ bool MipsFastISel::SelectStore(const Ins
// See if we can handle this address.
Address Addr;
- if (!ComputeAddress(I->getOperand(1), Addr))
+ if (!computeAddress(I->getOperand(1), Addr))
return false;
- if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
+ if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
return false;
return true;
}
-bool MipsFastISel::SelectRet(const Instruction *I) {
+bool MipsFastISel::selectRet(const Instruction *I) {
const ReturnInst *Ret = cast<ReturnInst>(I);
if (!FuncInfo.CanLowerReturn)
@@ -445,12 +471,12 @@ bool MipsFastISel::SelectRet(const Instr
if (Ret->getNumOperands() > 0) {
return false;
}
- EmitInst(Mips::RetRA);
+ emitInst(Mips::RetRA);
return true;
}
// Attempt to fast-select a floating-point extend instruction.
-bool MipsFastISel::SelectFPExt(const Instruction *I) {
+bool MipsFastISel::selectFPExt(const Instruction *I) {
if (UnsupportedFPMode)
return false;
Value *Src = I->getOperand(0);
@@ -467,13 +493,13 @@ bool MipsFastISel::SelectFPExt(const Ins
return false;
unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
- EmitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
+ emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
updateValueMap(I, DestReg);
return true;
}
// Attempt to fast-select a floating-point truncate instruction.
-bool MipsFastISel::SelectFPTrunc(const Instruction *I) {
+bool MipsFastISel::selectFPTrunc(const Instruction *I) {
if (UnsupportedFPMode)
return false;
Value *Src = I->getOperand(0);
@@ -491,12 +517,12 @@ bool MipsFastISel::SelectFPTrunc(const I
if (!DestReg)
return false;
- EmitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
+ emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
updateValueMap(I, DestReg);
return true;
}
-bool MipsFastISel::SelectIntExt(const Instruction *I) {
+bool MipsFastISel::selectIntExt(const Instruction *I) {
Type *DestTy = I->getType();
Value *Src = I->getOperand(0);
Type *SrcTy = Src->getType();
@@ -518,13 +544,13 @@ bool MipsFastISel::SelectIntExt(const In
MVT DestVT = DestEVT.getSimpleVT();
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
- if (!EmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
+ if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
return false;
updateValueMap(I, ResultReg);
return true;
}
-bool MipsFastISel::SelectTrunc(const Instruction *I) {
+bool MipsFastISel::selectTrunc(const Instruction *I) {
// The high bits for a type smaller than the register size are assumed to be
// undefined.
Value *Op = I->getOperand(0);
@@ -549,7 +575,7 @@ bool MipsFastISel::SelectTrunc(const Ins
}
// Attempt to fast-select a floating-point-to-integer conversion.
-bool MipsFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
+bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
if (UnsupportedFPMode)
return false;
MVT DstVT, SrcVT;
@@ -587,9 +613,9 @@ bool MipsFastISel::SelectFPToI(const Ins
Opc = Mips::TRUNC_W_D32;
// Generate the convert.
- EmitInst(Opc, TempReg).addReg(SrcReg);
+ emitInst(Opc, TempReg).addReg(SrcReg);
- EmitInst(Mips::MFC1, DestReg).addReg(TempReg);
+ emitInst(Mips::MFC1, DestReg).addReg(TempReg);
updateValueMap(I, DestReg);
return true;
@@ -599,7 +625,7 @@ bool MipsFastISel::SelectFPToI(const Ins
// end up with redundant "andi" instructions after the sequences emitted below.
// We should try and solve this issue in the future.
//
-bool MipsFastISel::EmitCmp(unsigned ResultReg, const CmpInst *CI) {
+bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
bool IsUnsigned = CI->isUnsigned();
unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
@@ -615,54 +641,54 @@ bool MipsFastISel::EmitCmp(unsigned Resu
return false;
case CmpInst::ICMP_EQ: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
- EmitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
+ emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
break;
}
case CmpInst::ICMP_NE: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
- EmitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
+ emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
break;
}
case CmpInst::ICMP_UGT: {
- EmitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
+ emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
break;
}
case CmpInst::ICMP_ULT: {
- EmitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
break;
}
case CmpInst::ICMP_UGE: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
- EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
break;
}
case CmpInst::ICMP_ULE: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
- EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
+ emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
break;
}
case CmpInst::ICMP_SGT: {
- EmitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
+ emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
break;
}
case CmpInst::ICMP_SLT: {
- EmitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
break;
}
case CmpInst::ICMP_SGE: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
- EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
+ emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
break;
}
case CmpInst::ICMP_SLE: {
unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
- EmitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
+ emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
+ emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
break;
}
case CmpInst::FCMP_OEQ:
@@ -708,11 +734,11 @@ bool MipsFastISel::EmitCmp(unsigned Resu
}
unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
- EmitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
- EmitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
- EmitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
+ emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
+ emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
+ emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
Mips::FCC0, RegState::ImplicitDefine);
- MachineInstrBuilder MI = EmitInst(CondMovOpc, ResultReg)
+ MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
.addReg(RegWithOne)
.addReg(Mips::FCC0)
.addReg(RegWithZero, RegState::Implicit);
@@ -723,10 +749,10 @@ bool MipsFastISel::EmitCmp(unsigned Resu
return true;
}
-bool MipsFastISel::SelectCmp(const Instruction *I) {
+bool MipsFastISel::selectCmp(const Instruction *I) {
const CmpInst *CI = cast<CmpInst>(I);
unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
- if (!EmitCmp(ResultReg, CI))
+ if (!emitCmp(ResultReg, CI))
return false;
updateValueMap(I, ResultReg);
return true;
@@ -739,56 +765,56 @@ bool MipsFastISel::fastSelectInstruction
default:
break;
case Instruction::Load:
- return SelectLoad(I);
+ return selectLoad(I);
case Instruction::Store:
- return SelectStore(I);
+ return selectStore(I);
case Instruction::Br:
- return SelectBranch(I);
+ return selectBranch(I);
case Instruction::Ret:
- return SelectRet(I);
+ return selectRet(I);
case Instruction::Trunc:
- return SelectTrunc(I);
+ return selectTrunc(I);
case Instruction::ZExt:
case Instruction::SExt:
- return SelectIntExt(I);
+ return selectIntExt(I);
case Instruction::FPTrunc:
- return SelectFPTrunc(I);
+ return selectFPTrunc(I);
case Instruction::FPExt:
- return SelectFPExt(I);
+ return selectFPExt(I);
case Instruction::FPToSI:
- return SelectFPToI(I, /*isSigned*/ true);
+ return selectFPToInt(I, /*isSigned*/ true);
case Instruction::FPToUI:
- return SelectFPToI(I, /*isSigned*/ false);
+ return selectFPToInt(I, /*isSigned*/ false);
case Instruction::ICmp:
case Instruction::FCmp:
- return SelectCmp(I);
+ return selectCmp(I);
}
return false;
}
-unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) {
+unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
if (UnsupportedFPMode)
return 0;
int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
if (VT == MVT::f32) {
const TargetRegisterClass *RC = &Mips::FGR32RegClass;
unsigned DestReg = createResultReg(RC);
- unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass);
- EmitInst(Mips::MTC1, DestReg).addReg(TempReg);
+ unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
+ emitInst(Mips::MTC1, DestReg).addReg(TempReg);
return DestReg;
} else if (VT == MVT::f64) {
const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
unsigned DestReg = createResultReg(RC);
- unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
+ unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
unsigned TempReg2 =
- Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
- EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
+ materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
+ emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
return DestReg;
}
return 0;
}
-unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) {
+unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
// For now 32-bit only.
if (VT != MVT::i32)
return 0;
@@ -799,13 +825,13 @@ unsigned MipsFastISel::MaterializeGV(con
// TLS not supported at this time.
if (IsThreadLocal)
return 0;
- EmitInst(Mips::LW, DestReg)
+ emitInst(Mips::LW, DestReg)
.addReg(MFI->getGlobalBaseReg())
.addGlobalAddress(GV, 0, MipsII::MO_GOT);
if ((GV->hasInternalLinkage() ||
(GV->hasLocalLinkage() && !isa<Function>(GV)))) {
unsigned TempReg = createResultReg(RC);
- EmitInst(Mips::ADDiu, TempReg)
+ emitInst(Mips::ADDiu, TempReg)
.addReg(DestReg)
.addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
DestReg = TempReg;
@@ -813,7 +839,7 @@ unsigned MipsFastISel::MaterializeGV(con
return DestReg;
}
-unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) {
+unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
return 0;
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
@@ -823,19 +849,19 @@ unsigned MipsFastISel::MaterializeInt(co
Imm = CI->getSExtValue();
else
Imm = CI->getZExtValue();
- return Materialize32BitInt(Imm, RC);
+ return materialize32BitInt(Imm, RC);
}
-unsigned MipsFastISel::Materialize32BitInt(int64_t Imm,
+unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
const TargetRegisterClass *RC) {
unsigned ResultReg = createResultReg(RC);
if (isInt<16>(Imm)) {
unsigned Opc = Mips::ADDiu;
- EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
+ emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
return ResultReg;
} else if (isUInt<16>(Imm)) {
- EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
+ emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
return ResultReg;
}
unsigned Lo = Imm & 0xFFFF;
@@ -843,14 +869,13 @@ unsigned MipsFastISel::Materialize32BitI
if (Lo) {
// Both Lo and Hi have nonzero bits.
unsigned TmpReg = createResultReg(RC);
- EmitInst(Mips::LUi, TmpReg).addImm(Hi);
- EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
+ emitInst(Mips::LUi, TmpReg).addImm(Hi);
+ emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
} else {
- EmitInst(Mips::LUi, ResultReg).addImm(Hi);
+ emitInst(Mips::LUi, ResultReg).addImm(Hi);
}
return ResultReg;
}
-}
namespace llvm {
FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
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