[PATCH] [llvm] [Hexagon] Adding tests, TableGen entries, and code for emitting add opcode.
Rafael Avila de Espindola
rafael.espindola at gmail.com
Fri Oct 10 21:03:50 PDT 2014
Sent from my iPhone
> On Oct 10, 2014, at 19:01, "colinl at codeaurora.org" <colinl at codeaurora.org> wrote:
> I think I understand the reason for the request now. It sounds like you're saying the translation between assembly and machine code is most efficiently and compactly represented by assembling or disassembling and since we have a tool for that, it would be nice to use it. That logic makes sense.
> I factored the unit test and it seems like they can be represented in a compact form which might satisfy the terseness request.
> If this change is still rejected Sid is investigating disassembler patches though it make take a few to get all the required parts in place.
Please do try to use the disassembler. It is silly to have to write c++ code to check the encoding of an instruction, specially when all other architectures use llvm-mc.
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