[PATCH] [AArch64] Add workaround for Cortex-A53 erratum (835769)

James Molloy james.molloy at arm.com
Fri Oct 10 07:41:45 PDT 2014

Hi Bradley,

> The rationale behind this name is that this phase isn't an A53 specific phase, it's a phase that addresses an A53 erratum. In a big-little system you may well want this phase enabled for A57 code.

Sorry, I'm not convinced by that rationale. By the same reasoning, the FP Load balancing for A57 might be applied to code with -mcpu=cortex-a53 because it may run on  a big.LITTLE system and has more impact for the big core than the little.

>> It doesn't seem right to continue with PrevInstr being nullptr.
> I've added an assert to getLastNonPseudo since if we have a block we've fallen through we expect to find an instruction. If getBBFallenThrough returns nullptr it means there was no fallen through block, hence PrevInstr being nullptr is valid in this case, meaning we have no previous instruction yet (the loop will then just go to the next interation where it does have one).

The case I was concerned about is if we had a fallthrough block, but that block contained only pseudo instructions. Do you handle that case correctly? You'd need to unwind through the fallthroughs until one contained a non-pseudo, I'd have thought.


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