[PATCH] R600/SI: Legalize INSERT_SUBREG instructions during PostISelFolding

[Matt Arsenault]

On 10/07/2014 05:11 PM, Tom Stellard wrote:
> On Tue, Oct 07, 2014 at 12:07:02AM -0700, Matt Arsenault wrote:
>> >
>> >On Oct 3, 2014, at 8:38 AM, Tom Stellard<thomas.stellard at amd.com>  wrote:
>> >
>>> > >LLVM assumes INSERT_SUBREG will always have register operands, so
>>> > >we need to legalize non-register operands, like FrameIndexes, to
>>> > >avoid random assertion failures.
>>> > >---
>>> > >lib/Target/R600/SIISelLowering.cpp | 27 +++++++++++++++++++++++++++
>>> > >test/CodeGen/R600/insert_subreg.ll | 15 +++++++++++++++
>>> > >2 files changed, 42 insertions(+)
>>> > >create mode 100644 test/CodeGen/R600/insert_subreg.ll
>>> > >
>>> > >diff --git a/lib/Target/R600/SIISelLowering.cpp b/lib/Target/R600/SIISelLowering.cpp
>>> > >index f042aaa..4c0d22d 100644
>>> > >--- a/lib/Target/R600/SIISelLowering.cpp
>>> > >+++ b/lib/Target/R600/SIISelLowering.cpp
>>> > >@@ -1923,6 +1923,30 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
>>> > >   }
>>> > >}
>>> > >
>>> > >+/// \brief Legalize INSERT_SUBREG instructions with frame index operands.
>>> > >+/// LLVM assumes that all INSERT_SUBREG inputs are registers.
>>> > >+static void LegalizeInsertSubreg(MachineSDNode *InsertSubreg,
>>> > >+                                 SelectionDAG &DAG) {
>> >
>> >Current convention for new code is function names start with a lowercase letter
>> >
>>> > >+
>>> > >+  assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
>>> > >+
>>> > >+  SmallVector <SDValue, 8> Ops;
>> >Extra space between SmallVector and <
>> >
>>> > >+  for (unsigned i = 0; i < 2; ++i) {
>>> > >+    if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) {
>>> > >+      Ops.push_back(InsertSubreg->getOperand(i));
>>> > >+      continue;
>>> > >+    }
>>> > >+
>>> > >+    SDLoc DL(InsertSubreg);
>>> > >+    Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
>>> > >+                                     InsertSubreg->getOperand(i).getValueType(),
>>> > >+                                     InsertSubreg->getOperand(i)), 0));
>>> > >+  }
>>> > >+
>>> > >+  DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1],
>>> > >+                         InsertSubreg->getOperand(2));
>>> > >+}
>>> > >+
>>> > >/// \brief Fold the instructions after selecting them.
>>> > >SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
>>> > >                                           SelectionDAG &DAG) const {
>>> > >@@ -1933,6 +1957,9 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
>>> > >   if (TII->isMIMG(Node->getMachineOpcode()))
>>> > >     adjustWritemask(Node, DAG);
>>> > >
>>> > >+  if (Node->getMachineOpcode() == AMDGPU::INSERT_SUBREG)
>>> > >+    LegalizeInsertSubreg(Node, DAG);
>> >
>> >I think you can just return here, since there isn’t really anything legalizeOperands needs to do for insert_subreg
>> >
>>> > >+
>>> > >   return legalizeOperands(Node, DAG);
>>> > >}
>>> > >
>>> > >diff --git a/test/CodeGen/R600/insert_subreg.ll b/test/CodeGen/R600/insert_subreg.ll
>>> > >new file mode 100644
>>> > >index 0000000..c9b22ec
>>> > >--- /dev/null
>>> > >+++ b/test/CodeGen/R600/insert_subreg.ll
>>> > >@@ -0,0 +1,15 @@
>>> > >+; RUN: llc -march=r600 -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s
>>> > >+
>>> > >+; Test that INSERT_SUBREG instructions don't have non-register operands after
>>> > >+; instruction selection.
>> >
>> >If it’s not testing anything no reason to use FileCheck
>> >
>>> > >+
>>> > >+; Make sure this doesn't crash
>>> > >+; CHECK-LABEL: test:
>>> > >+define void @test(i64 addrspace(1)* %out) {
>>> > >+entry:
>>> > >+  %tmp0 = alloca [16 x i32]
>>> > >+  %tmp1 = ptrtoint [16 x i32]* %tmp0 to i32
>>> > >+  %tmp2 = sext i32 %tmp1 to i64
>>> > >+  store i64 %tmp2, i64 addrspace(1)* %out
>>> > >+  ret void
>>> > >+}
>>> > >-- 
>>> > >1.8.5.5
>>> > >
> Hi Matt,
>
> Here is an updated patch, plus a similar fix for CopyToReg nodes.
>
> -Tom
LGTM
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