[PATCH] R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()

[Matt Arsenault]

On Oct 6, 2014, at 12:29 PM, Tom Stellard <thomas.stellard at amd.com> wrote:

> Added a FIXME coment instead, we need to handle the case where the
> two DS instructions being compared have different numbers of operands.
> ---
> lib/Target/R600/SIInstrInfo.cpp |  5 ++++-
> test/CodeGen/R600/load.ll       | 18 ++++++++++++++++++
> 2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp
> index af2177a..fc2c63d 100644
> --- a/lib/Target/R600/SIInstrInfo.cpp
> +++ b/lib/Target/R600/SIInstrInfo.cpp
> @@ -88,7 +88,10 @@ bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
>     return false;
> 
>   if (isDS(Opc0) && isDS(Opc1)) {
> -    assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1));
> +
> +    // FIXME: Handle this case:
> +    if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
> +      return false;
> 
>     // Check base reg.
>     if (Load0->getOperand(1) != Load1->getOperand(1))
> diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
> index d92ade1..ff489b5 100644
> --- a/test/CodeGen/R600/load.ll
> +++ b/test/CodeGen/R600/load.ll
> @@ -701,3 +701,21 @@ entry:
>   store <2 x float> %0, <2 x float> addrspace(1)* %out
>   ret void
> }
> +
> +; Test loading a i32 and v2i32 value from the same base pointer.
> +; FUNC-LABEL: {{^}}load_i32_v2i32_local:
> +; R600-CHECK: LDS_READ_RET
> +; R600-CHECK: LDS_READ_RET
> +; R600-CHECK: LDS_READ_RET
> +; SI-CHECK-DAG: DS_READ_B32
> +; SI-CHECK-DAG: DS_READ2_B32
> +define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) {
> +  %scalar = load i32 addrspace(3)* %in
> +  %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)*
> +  %vec_ptr = getelementptr <2 x i32> addrspace(3)* %tmp0, i32 2
> +  %vec0 = load <2 x i32> addrspace(3)* %vec_ptr, align 4
> +  %vec1 = insertelement <2 x i32> <i32 0, i32 0>, i32 %scalar, i32 0
> +  %vec = add <2 x i32> %vec0, %vec1
> +  store <2 x i32> %vec, <2 x i32> addrspace(1)* %out
> +  ret void
> +}
> -- 
> 1.8.5.5
> 
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LGTM